EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 328

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

9
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1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9.2.3.7 Transmit Descriptor Processor Queues
9.2.3.8 Transmit Descriptor Queue
The transmit descriptor processor uses two circular queues in Host memory to manage the
transfer of transmit data frame. The transmit descriptor queue is used to pass descriptors of
user's data buffers from the Host to the MAC. The transmit status queue is used to pass
information on the MAC's use of the data buffer back to the Host. Keeping these queues
separate enables the use of burst transfers to and from the queues, reducing the overall
amount of bus traffic and avoiding some potential latency problem.
The Transmit descriptors are passed from the Host to the MAC via the Transmit descriptor
queue. The Transmit descriptor queue is a circular queue occupying a contiguous area of
memory. The location and size of the queue are set at initialization by the Host writing to the
Transmit Descriptor Queue Base Address Register and the Transmit Descriptor Queue Base
Length. The base address must point to a word aligned memory location. The Transmit
Descriptor Queue Base Length is set to the length in bytes of the queue. The length should
be an integral number of descriptors and must not exceed 64 Kbytes total. The Transmit
descriptor current address must also be set at initialization to point to the first descriptor to be
used. This would normally be the first entry (same value as the base address).
Following initialization, the MAC will start to use descriptors from the Current Descriptor
Address, wrapping back to the base pointer whenever the end of the queue is reached. In
normal operation the Host should not need to access these registers after the initialization.
The management of the descriptors is handled via the Transmit Descriptor Enqueue register.
Enqueueing descriptors is the process of adding descriptors to an existing queue. This is
achieved in transmit by writing the number of additional descriptors to the Transmit Descriptor
Enqueue register. The written value will be added to the previous value to keep a running
total, as descriptors are read by the MAC, the total is adjusted. The running total is available
by reading the enqueue register. One frame may be described by more than one descriptor,
but the final descriptor will contain the EOF bit. Not all the descriptors for a frame need to be
supplied at once.
No more than 255 descriptors may be added in one write. If a number greater than this needs
to be written. the write should be broken up into more than one operation (that is, to add 300
descriptors - first write 255, then write 45).
Copyright 2007 Cirrus Logic
DS785UM1