EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 690

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

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AC’97 Controller
EP93xx User’s Guide
and all modem data are at the same sampling rate. If the external codec supported the
following channels: PCM LEFT, PCM RIGHT, MODEM1, PCM CENTRE, PCM L
SURROUND, PCM R SURROUND, PCM LFE, MODEM2 and HSET, then the user would
have to program the transmit side of the controller so that all the audio data was in channel 1,
modem data in channel 2, and the HSET data in channel 3. The controller could also receive
MIC data at a different rate. This data would have to be stored in channel 4. The controller is
designed to allow any slot data to be stored into any channel the user wishes. If the external
codec supports more than 4 sample rates, the user will have to determine which sample rates
to allow.
The controller has four channels, which consist of a transmit FIFO, receive FIFO and their
associated control logic. The control logic can be configured to allow the FIFOs to accept any
data to or from any slot in a frame.
The receive part of each channel is controlled via its AC97RXCR register. This register
controls the following:
The transmit part of each channel is controlled via its AC97TXCR register. This register
controls the following:
Slot 0 for transmission is determined by the controller depending on the values in the
AC97TXCR register, the data request bits, and the FIFO having valid data to send. If a slot
does not have any data for transmission, the controller will fill the slot with zeros and set the
Tag bits as invalid.
If the external codec does not support the Data Request Disable bits/Variable Rate Extension
the bits will always be “0” meaning a sample rate of 48 kHz. As slots 1 and 2 are always
• Which slot data from the received frame is to be stored in the FIFO. The controller will
• The length of time before a timeout interrupt is generated.
• Whether the FIFO is enabled or not.
• The number of bits in the slot that is captured.
• Whether the channel is enabled to receive data or not.
• Which slot the data in the FIFO is to be transmitted in, the user must ensure that all the
• Whether the FIFO is enabled or not.
• The number of bits that need to be appended to the data from the CPU to make the word
• Whether the channel is enabled to transmit data or not.
• The transmit channel also supports variable sample rates via the Data Request Disable
not store any other slots than those specified in these registers. The user must ensure
that all slot data stored in the FIFO is at the same sampling rate.
data in the FIFO is intended for slots with the same sampling rate. The data must be
supplied lowest slot number first.
20 bits.
Slots from the external codec in slot 1. The data request bits for all audio and modem
data are expected to occur at the same time.
Copyright 2007 Cirrus Logic
DS785UM1