EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 454

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

11
11-14
Universal Serial Bus Host Controller
EP93xx User’s Guide
BLE:
HCFS:
IR:
RWC:
Copyright 2007 Cirrus Logic
BulkListEnable:
This bit is set to enable the processing of the Bulk list in
the next Frame. If cleared by HCD, processing of the Bulk
list does not occur after the next SOF. HC checks this bit
whenever it determines to process the list. When disabled,
HCD may modify the list. If HcBulkCurrentED is pointing to
an ED to be removed, HCD must advance the pointer by
updating HcBulkCurrentED before re-enabling processing
of the list.
HostControllerFunctionalState:
A transition to USBOPERATIONAL from another state
causes SOF generation to begin 1 ms later. HCD may
determine whether HC has begun sending SOFs by
reading the StartofFrame field of HcInterruptStatus. This
field may be changed by HC only when in the
USBSUSPEND state. HC may move from the
USBSUSPEND state to the USBRESUME state after
detecting the resume signaling from a downstream port.
HC enters USBSUSPEND after a software reset, whereas
it enters USBRESET after a hardware reset. The latter
also resets the Root Hub and asserts subsequent reset
signaling to downstream ports.
0 0 = USBRESET
0 1 = USBRESUME
1 0 = USBOPERATIONAL
1 1 = USBSUSPEND
InterruptRouting:
This bit determines the routing of interrupts generated by
events registered in HcInterruptStatus. If clear, all
interrupts are routed to the normal host bus interrupt
mechanism. If set, interrupts are routed to the System
Management Interrupt. HCD clears this bit upon a
hardware reset, but it does not alter this bit upon a
software reset. HCD uses this bit as a tag to indicate the
ownership of HC.
RemoteWakeupConnected:
This bit indicates whether HC supports remote wakeup
signaling. If remote wakeup is supported and used by the
system it is the responsibility of system firmware to set this
bit during POST. HC clears the bit upon a hardware reset
but does not alter it upon a software reset. Remote
wakeup signaling of the host system is host-bus-specific
and is not described in this specification.
DS785UM1