EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 194
![IC ARM9 SOC PROCESSOR 208LQFP](/photos/12/23/122385/mfg_ep9302_parts_sml.jpg)
EP9302-CQZ
Manufacturer Part Number
EP9302-CQZ
Description
IC ARM9 SOC PROCESSOR 208LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9302-IQZ.pdf
(42 pages)
3.EP9302-IQZ.pdf
(4 pages)
4.EP9302-IQZ.pdf
(40 pages)
Specifications of EP9302-CQZ
Program Memory Type
ROMless
Package / Case
208-LQFP
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Data Ram Size
16 bit
Interface Type
USB, USART, SPI
Maximum Clock Frequency
200 MHz
Number Of Programmable I/os
37
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9302A-Z
Controller Family/series
(ARM9)
No. Of I/o's
19
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1132 - KIT DEVELOPMENT EP9302 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1137
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
EP9302-CQZ
Manufacturer:
Cirrus
Quantity:
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EP9302-CQZ
Manufacturer:
ALTERA
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- EP9307-CRZ PDF datasheet
- EP9302-IQZ PDF datasheet #2
- EP9302-IQZ PDF datasheet #3
- EP9302-IQZ PDF datasheet #4
- Current page: 194 of 824
- Download datasheet (13Mb)
7
7-12
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7.4.7 Pixel Shift Logic
data into the unused LSBs of the bus to support the full color intensity range. This part of the
multiplexing circuitry actually occurs before the blink logic stage. Once selected and
conditioned, output data is sent to the pixel shift logic and the YCrCb logic. The data is further
conditioned with blanking in another pipeline operation before being sent to a color DAC.
The pixel shifting logic on the output of the Video controller circuitry allows for reduced
external data and clock rates by performing multiple pixel transfers in parallel. The output can
be programmed to transfer a single pixel mapped to an 18-bit pixel output per clock (triple 6
RGB on 18 active data lines), 2 pixels per clock up to 9 bits wide each (18 pixel data lines
active), 4 pixels per clock up to 4 bits wide each (16 pixel data lines active), or 8 pixels per
clock up to 2 bits wide each (16 pixel data lines active). The interface can be programmed to
output 2 2/3 - 3-bit pixels on the lower 8 bits of the bus per pixel clock. The interface can be
programmed to operate in dual scan 2 2/3 pixel mode, placing 2 2/3 pixels from the upper
and lower halves of the screen on the lower 8 bits of the bus and the next 8 bits of the bus per
clock respectively. In dual scan mode, selected by writing DSCAN = ‘1’ to the
register, every other pixel in the pipeline is from the other half of the display. Therefore, the
dual scan output transfer modes that are supported are 1 upper/1 lower pixel, 2 upper/2 lower
pixels, and 4 upper/4 lower pixels corresponding to the 2 pixels per clock, 4 pixels per clock
and 8 pixels per clock modes.
Table 7-3
and the color mode “C” value (color value) in the
shows output pixel transfer modes based on the shift mode “S” value (shift value)
Copyright 2007 Cirrus Logic
“PixelMode”
register:
“PixelMode”
DS785UM1
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