EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 459

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

HcInterruptDisable
DS785UM1
MIE
31
15
Address:
Default:
Definition:
Bit Descriptions:
OC
30
14
29
13
28
12
FNO:
RHSC:
OC:
MIE:
0x8002_0014
0x0000_0000
Disables interrupt sources.
RSVD:
SO:
WDH:
SF:
RD:
UE:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
FrameNumberOverflow. Enable interrupt generation due
to Frame Number Overflow.
RootHubStatusChange. Enable interrupt generation due to
Root Hub Status Change.
OwnershipChange. Enable interrupt generation due to
Ownership Change.
Master Interrupt Enable. A zero written to this field is
ignored by HC. A one written to this field enables interrupt
generation due to events specified in the other bits of this
register. This is used by HCD as a Master Interrupt
Enable.
Reserved. Unknown During Read.
SchedulingOverrun: Disable interrupt generation due to
Scheduling Overrun.
WritebackDoneHead: Disable interrupt generation due to
HcDoneHead Writeback.
StartofFrame: Disable interrupt generation due to Start of
Frame.
ResumeDetected: Disable interrupt generation due to
Resume Detect.
UnrecoverableError: Disable interrupt generation due to
Unrecoverable Error.
24
8
23
7
RSVD
RHSC
22
6
FNO
21
5
Universal Serial Bus Host Controller
UE
20
4
RD
19
3
EP93xx User’s Guide
SF
18
2
WDH
17
1
11-19
SO
16
0
11