EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 532

IC ARM9 SOC PROCESSOR 208LQFP

EP9302-CQZ

Manufacturer Part Number
EP9302-CQZ
Description
IC ARM9 SOC PROCESSOR 208LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9302-CQZ

Program Memory Type
ROMless
Package / Case
208-LQFP
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Data Ram Size
16 bit
Interface Type
USB, USART, SPI
Maximum Clock Frequency
200 MHz
Number Of Programmable I/os
37
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9302A-Z
Controller Family/series
(ARM9)
No. Of I/o's
19
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1132 - KIT DEVELOPMENT EP9302 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1137

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14
14-10
UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide
The receiver utilizes a digital PLL to synchronize to the incoming encoded bit stream. The
digital PLL should always successfully lock on to an incoming data stream within two bytes
provided that the first two bits of the first byte are either “01” or “10”. Hence, at a minimum,
two bytes must precede the final opening flag to insure that the HDLC receiver sees the
packet. To meet this requirement, the simplest approach is to insure that at least three
opening flags are received if the packet is Manchester encoded. (Note that to meet this
requirement when transmitting, field HDLC1Ctrl.FLAG should be set to 0010b.)
Three bits in various combination determine how an external or internal clock may be used
along with NRZ data. The clock will have a period equal to the bit period of the data stream,
and it is expected that the internal or external receiver will sample the bit at or near the rising
edge of this clock.
To generate an internal clock suitable for sending along with the transmitted data, set
UART1HDLCCtrl.TXCM and UART1HDLCCtrl.CMAS. To make the receiver use the same
internal clock, set UART1HDLCCtrl.RXCM. To make the receiver use an externally generated
clock, clear UART1HDLCCtrl.CMAS, but set UART1HDLCCtrl.RXCM.
To force the transmitter to use the same external clock, also set UART1HDLCCtrl.TXCM. The
clock is either internal or external, that is, the receiver cannot use an external clock while the
transmitter generates and sends an internal one. Refer to the documentation for the
DeviceCfg register in Syscon for the use and routing of HDLC clocks to or from external pins
on the device.
The internal clock is generated by the transmitter only while it is sending data or flags; the
clock is not generated while the transmitter is idle. For this reason, another transmitter which
expects to use this clock to at any time send its own packets cannot reliably do so. To insure
that a clock is continuously generated, the IDLE bit in the UART1HDLCCtrl register may be
set, which causes this transmitter to continuously send flags between packets instead of
going idle.
Table 14-2
CMAS TXCM RXCM TXENC RXENC SYNC
1
-
-
-
-
-
-
-
-
-
summarizes the legal HDLC mode configurations.
1
1
1
-
-
-
-
-
-
-
UART1HDLCCtrl Bits Set
1
1
-
-
-
-
-
-
-
-
Table 14-2. Legal HDLC Mode Configurations
1
1
1
-
-
-
-
-
-
-
Copyright 2007 Cirrus Logic
1
1
1
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
1
-
Asynchronous NRZ
Synchronous NRZ
Synchronous NRZ
Synchronous NRZ
Transmit Mode
External clock
External clock
Internal clock
Manchester
Manchester
Manchester
Asynchronous NRZ
Synchronous NRZ
Synchronous NRZ
Synchronous NRZ
Synchronous NRZ
Receive Mode
External clock
External clock
Manchester
Manchester
Manchester
DS785UM1

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