EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 528

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

14
14-6
UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide
14.2.2.1 Error Bits
14.2.2.2 Disabling the FIFOs
14.2.2.3 System/diagnostic Loopback Testing
14.2.2.4 UART Character Frame
Three error bits are stored in bits [10:8] of the receive FIFO, and are associated with a
particular character. See
error but it is not associated with a particular character in the receive FIFO. The overrun error
is set when the FIFO is full and the next character has been completely received in the shift
register. The data in the shift register is overwritten but it is not written into the FIFO.
Additionally, it is possible to disable the FIFOs. In this case, the transmit and receive sides of
the UART have 1-byte holding registers (the bottom entry of the FIFOs). The overrun bit is set
when a word has been received and the previous one was not yet read. In this
implementation, the FIFOs are not physically disabled, but the flags are manipulated to give
the illusion of a 1-byte register.
It is possible to perform loopback testing for UART data by setting the Loop Back Enable
(LBE) bit to 1 in the control register UARTxCtrl (bit 7).
Data transmitted on UARTTXD output will be received on the UARTRXD input.
The UART character frame is shown in
FIFO bit
7:0
10
9
8
Table
Table 14-1. Receive FIFO Bit Functions
Figure 14-2. UART Character Frame
Figure 14-3. UART Character Frame
Copyright 2007 Cirrus Logic
14-1. There is an additional error which indicates an overrun
Figure
14-2:
Received data
Framing error
Break error
Parity error
Function
DS785UM1