EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 349

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

DS785UM1
The following procedure will correctly set the SelfCtl register value:
1. Read the value of SelfCtl
2. Clear PSPRS bit in SelfCtl Register.
3. Read/write PHY registers.
4. Restore the old value to SelfCtl.
RWP:
GPO0:
PUWE:
PDWE:
MIIL:
Copyright 2007 Cirrus Logic
Remote Wake Pin. This bit reflects the current state of the
REMWAKE pin. Following a system power up, caused by
a Remote Wake-up frame being detected by the MAC, this
bit is set.
General Purpose Output 0. This bit directly controls the
GPO[0] pin. A “1” corresponds to a logic high on the pin.
Power Up Wake-up Enable. Setting the Power Up Wake-
up enable bit causes the MAC to enter the remote wake-
up mode, during normal operation (AHB bus powered up).
In this mode all receive frames that pass the destination
address filter are scanned for the remote wake-up pattern
(six bytes of 0xFF followed directly by sixteen consecutive
copies of the Individual address). When this pattern is
detected, the REMWAKE pin is driven high and Remote
Wake-up (Interrupt Status is set).
Power Down Wake-up Enable. Setting the Power Down
Wake-up Enable bit causes the MAC to enter the remote
wake-up mode when the AHB bus is powered down. In
this mode all receive frames that pass the destination
address filter are scanned for the remote wake-up pattern
(six bytes of FFh followed directly by sixteen consecutive
copies of the Individual address). When this pattern is
detected, the REMWAKE pin is driven high, and can be
used to initiate a system power up, the state of the
REMWAKE pin is visible via the Remote Wake Pin bit of
this register.
MII Loopback. Setting the MII Loopback bit causes
transmit data to be diverted back into the receive data path
prior to the MII interface pins, the transmit data does not
appear on the MII bus and the receive data on the MII bus
is ignored. The clock for the transmit and receive data is
derived from the AHB CLK in the loopback mode. It is
strongly recommended that TXCLK and RXCLK come
from a single clock source with minimum skew in order to
ensure the proper operation of the loopback test. For
reliable operation a software reset should be issued when
the MII loopback bit is changed.
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
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