EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 434
EP9302-CQZ
Manufacturer Part Number
EP9302-CQZ
Description
IC ARM9 SOC PROCESSOR 208LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9302-IQZ.pdf
(42 pages)
3.EP9302-IQZ.pdf
(4 pages)
4.EP9302-IQZ.pdf
(40 pages)
Specifications of EP9302-CQZ
Program Memory Type
ROMless
Package / Case
208-LQFP
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Data Ram Size
16 bit
Interface Type
USB, USART, SPI
Maximum Clock Frequency
200 MHz
Number Of Programmable I/os
37
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9302A-Z
Controller Family/series
(ARM9)
No. Of I/o's
19
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1132 - KIT DEVELOPMENT EP9302 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1137
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9302-CQZ
Manufacturer:
Cirrus
Quantity:
3 295
Company:
Part Number:
EP9302-CQZ
Manufacturer:
ALTERA
Quantity:
672
Part Number:
EP9302-CQZ
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
- EP9307-CRZ PDF datasheet
- EP9302-IQZ PDF datasheet #2
- EP9302-IQZ PDF datasheet #3
- EP9302-IQZ PDF datasheet #4
- Current page: 434 of 824
- Download datasheet (13Mb)
10
10-40
DMA Controller
EP93xx User’s Guide
DREQS:
Copyright 2007 Cirrus Logic
The NextBuffer status bit can be used in conjunction with
the CurrentState status bits to determine the active buffer
according to the following rules:
If CurrentState[4:3] = DMA_BUF_ON and NextBuffer = 1
then Buffer0 is the active buffer.
If CurrentState[4:3] = DMA_BUF_ON and NextBuffer = 0
then Buffer1 is the active buffer.
If CurrentState[4:3] = DMA_BUF_NEXT and NextBuffer =
0 then Buffer0 is the active buffer.
If CurrentState[4:3] = DMA_BUF_NEXT and NextBuffer =1
then Buffer1 is the active buffer.
DREQ Status - This bit reflects the status of the
synchronized external DMA Request signal or IDE/SSP
requests:
0 - No external DMA request is pending or, in the case of a
transfer without handshaking, the request is not validated
yet, the wait state counter is running.
1 - An external DMA request or a validated IDE/SSP or
external peripheral without handshaking request is
pending.
DREQS can be polled by software at any time. It can, for
example, be used to determine whether or not the DMA
needs to be set up for a transfer when the DMA is in the
STALL state and is receiving DREQs, but the BCRx
registers have not been programmed. It is important to
notice that, in the case of a transfer without handshaking
(external DMA or IDE or SSP), DREQS might be clear if a
request is pending but is not validated as a result of a wait
state counter still running.
When the channel STATUS register is written with any 32-
bit value, this will cause the DREQS bit of the STATUS
register to be cleared. A write to the STATUS register only
affects the DREQS bit. If an edge is detected on DREQ
when no previous request is still pending in the DMA (that
is, DREQS clear), then the DREQS bit is set by the DMA
DS785UM1
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