EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 78

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

3
3-8
MaverickCrunch Co-Processor
EP93xx User’s Guide
3.2.1 Example 1
3.2.1.1 Setup Code
3.2.1.2 C Code
3.2.1.3 Accessing MaverickCrunch with ARM Co-Processor Instructions
3.2.1.4 MaverickCrunch Assembly Language Instructions
3.2 Programming Examples
The examples below show two algorithms, each implemented using the standard
programming languages and the MaverickCrunch instruction set.
Section
the same operation.
Section 3.2.1.2
assembly language, accessing the MaverickCrunch with ARM co-processor instructions.
Section 3.2.1.4
ldr
mov
str
register
ldr
to
orr
str
int num = 0;
for(num=0; num < 10; num++)
3.2.1.2,
num = num * 5;
loop
ldc p5, c0, [r0, #0x0]
ldc p5, c1, [r0, #0x4]
ldc p5, c2, [r0, #0x8]
ldc p5, c3, [r0, #0xc]
cdp p5, 1, c0, c0, c3, 0
cdp p5, 3, c0, c0, c2, 6
mrc p5, 0, r15 c0, c1, 4
blt loop
stc p5, c0, [r0, #0x0]
cfldr32 c0, [r0, #0x0]
cfldr32 c1, [r0, #0x4]
cfldr32 c2, [r0, #0x8]
cfldr32 c3, [r0, #0xc]
r1,
shows the program implemented in C code.
uses MaverickCrunch assembly language instructions.
r1,
r0,
r1,
r1,
r1,
Section
#0xaa
Section 3.2.1.1
[r0, #0x80]
=80930000
[r0, #0xc0]
r1, #0x00800000
[r0, #0x80]
3.2.1.3, and
Copyright 2007 Cirrus Logic
shows common setup code used by all three samples.
Section 3.2.1.4
; c0 <= c0 * 5
; c0 <= c0 - 1
; c0 < 10 ?
; data section preloaded with 0x0 (“num”)
; data section preloaded with 0xa
; data section preloaded with 0x1
; data section preloaded with 0x5
;
; data section preloaded with 0x0 (“num”)
; data section preloaded with 0xa
; data section preloaded with 0x1
; data section preloaded with 0x5
; enable MaverickCrunch co-processor
no, store result
; Syscon base address
; Turn on CPENA bit in DEVCFG register
; SW lock key
; unlock by writing key to SysSWLock
;
;
show three coding samples performing
yes
Section 3.2.1.3
uses ARM
DS785UM1