EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 313
![IC ARM9 SOC PROCESSOR 208LQFP](/photos/12/23/122385/mfg_ep9302_parts_sml.jpg)
EP9302-CQZ
Manufacturer Part Number
EP9302-CQZ
Description
IC ARM9 SOC PROCESSOR 208LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9302-IQZ.pdf
(42 pages)
3.EP9302-IQZ.pdf
(4 pages)
4.EP9302-IQZ.pdf
(40 pages)
Specifications of EP9302-CQZ
Program Memory Type
ROMless
Package / Case
208-LQFP
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Data Ram Size
16 bit
Interface Type
USB, USART, SPI
Maximum Clock Frequency
200 MHz
Number Of Programmable I/os
37
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9302A-Z
Controller Family/series
(ARM9)
No. Of I/o's
19
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1132 - KIT DEVELOPMENT EP9302 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1137
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Price
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- EP9307-CRZ PDF datasheet
- EP9302-IQZ PDF datasheet #2
- EP9302-IQZ PDF datasheet #3
- EP9302-IQZ PDF datasheet #4
- Current page: 313 of 824
- Download datasheet (13Mb)
DS785UM1
9.1.4.10 Rx Missed and Tx Collision Counters
9.1.4.11 Accessing the MII
To comply with the standard, pause frames should only be sent on full duplex links. The MAC
does not enforce this, it is left to the driver. If a pause frame is sent on a half duplex link, it is
subject to the normal half duplex collisions rules and retry attempts.
The format of a transmit pause frame is:
Bytes 1-6 - Destination address - this is the last Individual address (Address Filter Pointer =
6)
Bytes 7-12 - Source address - this is the first Individual address (Address Filter Pointer = 0)
Bytes 13-14 - Type field - this is defined in the Flow Control Format register
Bytes 15-16 - Opcode - set to 0x0001
Bytes 17-18 - Pause time - this is defined in the Flow Control Format register
Once the Host sets the Send Pause bit in TXCtl, it will remain set until the pause frame starts
transmission. Then the Send Pause clears and the Pause Busy bit is set and remains set
until the transmission is complete. No end of frame status is generated for pause frames.
There are three counters that help the software in recording events, transmit collisions,
receive missed frames, and receive runt frames. All three counters operate in similar ways.
When the appropriate events occur the counters are incremented. They are cleared following
a read of the count value. If a count is incremented such that the MSB is set, the
corresponding status bit in the Interrupt Status Register is set. An interrupt is generated at
this time if the corresponding enable bit is set in the Interrupt Enable Register. Once the
count is incremented to an all ones condition it will not be incremented further, it will remain in
this state until reset by a read operation.
This section describes the proper method to access the MII. It includes how to read/write
PHY registers, how to have the PHY perform auto-negotiation, and how to startup the PHY.
The bits MDCDIV in register SelfCtl are used to control the PHY's clock divisor. The default
value is 0x07, so the MDC clock frequency is HCLK divided by 8. This default value is correct
for most PHYs. However, to be safe, check the PHY's data sheet to make sure that this clock
frequency is correct.
The bit PSPRS in register SelfCtl is used to disable/enable Preamble Suppress for data
passed from the MAC to the PHY through the MDIO. If bit PSPRS is set, the preamble is
suppressed. In this case, the MAC won't prepend 32 bits of “1” to the data written to the PHY.
Since the MAC automatically prepends the preamble to data when in transmission mode, bit
PSPRS must be set while the MAC is transmitting frames. Otherwise, two preambles will be
prepended and cause a transmission failure. The default value of “1” is appropriate for
transmitting frames.
The MAC won't automatically prepend a preamble when not in transmission mode.
Therefore, if the MAC wants to read/write PHY registers, bit PSPRS may be cleared since
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9-11
9
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