DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 12

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.6.00 Oct.28.2004 page vi of xxiv
REJ09B0138-0600H
I t e m
19.18.2 Program-Verify Mode
Figure 19-48 Program/Program-
Verify Flowchart
22.3.6 Flash Memory
Characteristics
Table 22-21 Flash Memory
Characteristics (HD64F2398F20,
HD64F2398TE20)
Table 22-22 Flash Memory
Characteristics (HD64F2398F20T,
HD64F2398TE20T)
P a g e
639
724
726
Revision (See Manual for Details)
Figure 19-48 amended, note *6 added
Table 22-21 title amended
Table 22-22 added
Note: 7 Write Pulse Width
Note: Use a (z3) s write pulse for additional
Number of Writes (n)
Additional program data
Write pulse application subroutine
Reprogram data area
Wait (z1) s or (z2) s or (z3) s
Program data area
area (128 bytes)
Clear PSU bit in FLMCR1
programming.
Set PSU bit in FLMCR1
Sub-routine write pulse
Clear P bit in FLMCR1
(128 bytes)
(128 bytes)
1000
Set P bit in FLMCR1
998
999
10
11
12
13
1
2
3
4
5
6
7
8
9
.
.
.
RAM
Disable WDT
Enable WDT
Wait ( ) s
Wait (y) s
Wait ( ) s
End sub
Write Time (z) s
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z2
z2
z2
z2
.
.
.
*6
*5*6
*6
*6
Increment address
NG
Store 128-byte program data in program
data area consecutively to flash memory
additional program data area in RAM to
Write 128-byte data in RAM reprogram
Transfer reprogram data to reprogram
Additional program data computation
H'FF dummy write to verify address
Transfer additional program data to
Sequentially write 128-byte data in
data area and reprogram data area
additional program data area
Reprogram data computation
(z3 s additional write pulse)
Clear SWE bit in FLMCR1
Clear PV bit in FLMCR1
Set SWE bit in FLMCR1
Set PV bit in FLMCR1
Start of programming
End of programming
Read data = verify
Read verify data
(z1) s or (z2) s
data verification
flash memory
Write Pulse
Wait (x) s
Write pulse
Wait ( ) s
Wait ( ) s
completed?
Wait (
Wait (
data area
128-byte
m = 0
6
6
m = 0?
n = 1
data?
Start
n ?
n ?
OK
OK
OK
OK
OK
s
s
Sub-routine-call
NG
NG
NG
NG
*6
*6
*4
*1
See note 7 regarding pulse width
switching.
*6
*6
*6
*2
*4
*3
*4
*6
*1
*6
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
m = 1
Clear SWE bit in FLMCR1
Programming failure
Wait (
n
N?
OK
s
NG
n
n + 1
*6