DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 530

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Data Transfer Operations:
Rev.6.00 Oct.28.2004 page 500 of 1016
REJ09B0138-0600H
Multiprocessor serial data transmission
Figure 14-10 shows a sample flowchart for multiprocessor serial data transmission.
The following procedure should be used for multiprocessor serial data transmission.
Clear DR to 0 and set DDR to 1
Write transmit data to TDR and
Figure 14-10 Sample Multiprocessor Serial Transmission Flowchart
Read TDRE flag in SSR
Read TEND flag in SSR
Clear TE bit in SCR to 0
Clear TDRE flag to 0
set MPBT bit in SSR
All data transmitted?
Start transmission
Break output?
Initialization
TDRE= 1
TEND= 1
<End>
Yes
Yes
Yes
Yes
No
No
No
No
[1]
[2]
[3]
[4]
[1]
[2]
[3]
[4]
SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1,
a frame of 1s is output, and
transmission is enabled.
SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
Serial transmission continuation
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
possible, then write data to TDR,
and then clear the TDRE flag to
0. Checking and clearing of the
TDRE flag is automatic when the
DMAC or DTC is activated by a
transmit data empty interrupt
(TXI) request, and data is written
to TDR.
Break output at the end of serial
transmission:
To output a break in serial
transmission, set the port DDR to
1, clear DR to 0, then clear the
TE bit in SCR to 0.