DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 353

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.12.2
Table 9-21 shows the port E register configuration.
Table 9-21 Port E Registers
Notes: 1. Lower 16 bits of the address.
Port E Data Direction Register (PEDDR)
PEDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port E. PEDDR
cannot be read; if it is, an undefined value will be read.
PEDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Note: * Modes 6 and 7 are provided in the on-chip ROM version only.
Port E Data Register (PEDR)
PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE
Bit
Initial value :
R/W
Bit
Initial value :
R/W
Mode 7*
Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin
an input port.
Modes 4 to 6*
When 8-bit bus mode has been selected, port E pins function as I/O ports. Setting a PEDDR bit to 1 makes the
corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port.
When 16-bit bus mode has been selected, the input/output direction specification by PEDDR is ignored, and port E is
designated for data I/O.
For details of 8-bit and 16-bit bus modes, see section 6, Bus Controller.
2. PEPCR settings are prohibited in the ROMless version.
Register Configuration
Name
Port E data direction register
Port E data register
Port E register
Port E MOS pull-up control register*
:
:
:
:
PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR
PE7DR
R/W
W
7
0
7
0
PE6DR
R/W
W
6
0
6
0
PE5DR
R/W
W
5
0
5
0
2
PE4DR
R/W
W
PEPCR
Abbreviation
PEDDR
PEDR
PORTE
4
0
4
0
PE3DR
R/W
W
3
0
3
0
PE2DR
R/W
W
R/W
R
R/W
R/W
W
2
0
2
0
Initial Value
H'00
H'00
Undefined
H'00
PE1DR
R/W
W
Rev.6.00 Oct.28.2004 page 323 of 1016
1
0
1
0
7
to PE
PE0DR
R/W
W
0
0
0
0
0
).
Address*
H'FEBD
H'FF6D
H'FF5D
H'FF74
REJ09B0138-0600H
1