DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 193

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.11.3
Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the
bus and is currently operating, the bus is not necessarily transferred immediately. There are specific times at which each
bus master can relinquish the bus.
CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC or DMAC, the bus arbiter
transfers the bus to the bus master that issued the request. The timing for transfer of the bus is as follows:
DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated.
The DTC can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register
information write (3 states). It does not release the bus during a register information read (3 states), a single data transfer,
or a register information write (3 states).
DMAC: The DMAC sends the bus arbiter a request for the bus when an activation request is generated.
In the case of an external request in short address mode or normal mode, and in cycle steal mode, the DMAC releases the
bus after a single transfer.
In block transfer mode, it releases the bus after transfer of one block, and in burst mode, after completion of a transfer.
6.11.4
External bus release can be performed on completion of an external bus cycle. The RD signal, DRAM interface RAS and
CAS signals remain low until the end of the external bus cycle. Therefore, when external bus release is performed, the
RD, RAS, and CAS signals may change from the low level to the high-impedance state.
The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in
the case of a longword-size access, the bus is not transferred between the operations. See Appendix A.5, Bus States
during Instruction Execution, for timings at which the bus is not transferred.
If the CPU is in sleep mode, it transfers the bus immediately.
Bus Transfer Timing
External Bus Release Usage Note
Rev.6.00 Oct.28.2004 page 163 of 1016
REJ09B0138-0600H