DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 255

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 7-26 shows an example of DREQ level activated block transfer mode transfer.
DREQ pin sampling is performed every cycle, with the rising edge of the next ø cycle after the end of the DMABCR write
cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in
the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the dead cycle,
acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer
ends.
[1]
[2] [5]
[3] [6]
[4] [7]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Address bus
DMA control
Figure 7-26 Example of DREQ Level Activated Block Transfer Mode Transfer
Channel
DREQ
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising
edge of ø, and the request is held.
The request is cleared at the next bus break, and activation is started in the DMAC.
The DMA cycle is started.
Acceptance is resumed after the dead cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of ø, and the request is held.)
ø
Minimum of 2 cycles
Bus release
[1]
Request
Idle
[2]
Read
[3]
Request clear period
Transfer
DMA
source
read
Write
1 block transfer
Acceptance resumes
DMA
right
destination
Transfer
Dead
Minimum of 2 cycles
[4]
DMA
dead
Request
Idle
[5]
release
Bus
Read
[6]
Transfer
Request clear period
source
DMA
read
Write
1 block transfer
Rev.6.00 Oct.28.2004 page 225 of 1016
destination
Transfer
DMA
right
Dead
Acceptance resumes
DMA
dead
[7]
release
Idle
Bus
REJ09B0138-0600H