DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 145

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master to drop the bus request
signal (BREQ) in the external bus release state, when an internal bus master performs an external space access, or when a
refresh request is generated.
Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'01FFFF*
or external addresses.
Notes: 1. Reserved areas should not be accessed.
Bit 4—LCAS Select (LCASS): Write 0 to this bit when using the DRAM interface.
LCAS pin used for 2-CAS type DRAM interface LCAS signal. BREQO output and WAIT input cannot be used when
LCAS signal is used.
Bit 3—DACK Timing Select (DDS): Selects the DMAC single address transfer bus timing for the DRAM interface.
Bit 2—Reserved: Only 1 should be written to this bit.
Bit 1—Write Data Buffer Enable (WDBE): Selects whether or not the write buffer function is used for an external write
cycle or DMAC single address cycle.
2. Addresses H'010000 to H'01FFFF are in the H8S/2357. Addresses H'010000 to H'03FFFF are in the H8S/2398.
Bit 6
BREQOE
0
1
Bit 5
EAE
0
1
Bit 3
DDS
0
1
Bit 1
WDBE
0
1
Description
BREQO output disabled. BREQO can be used as I/O port.
BREQO output enabled.
Description
Addresses H'010000 to H'01FFFF*
Addresses H'010000 to H'01FFFF*
or a reserved area*
Description
When DMAC single address transfer is performed in DRAM space, full access is
always executed
DACK signal goes low from T
Burst access is possible when DMAC single address transfer is performed in DRAM
space
DACK signal goes low from T
Description
Write data buffer function not used
Write data buffer function used
1
(single-chip mode)
r
c1
or T
or T
1
2
2
2
cycle
are in on-chip ROM
are external addresses (external expansion mode)
cycle
Rev.6.00 Oct.28.2004 page 115 of 1016
2
are to be internal addresses
(Initial value)
(Initial value)
(Initial value)
(Initial value)
REJ09B0138-0600H