DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 884

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

TSR3—Timer Status Register 3
TCNT3—Timer Counter 3
Rev.6.00 Oct.28.2004 page 854 of 1016
REJ09B0138-0600H
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Note: * Can only be written with 0 for flag clearing.
:
:
:
:
:
:
—
—
7
1
R/W
15
0
—
—
6
1
R/W
14
0
R/W
—
—
5
0
13
0
R/W
Overflow Flag
R/(W)*
TCFV
12
0
1
0
H'FE85
4
0
[Setting condition]
When the TCNT value overflows (changes from H'FFFF to H'0000 )
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
R/W
11
0
R/(W)*
Input Capture/Output Compare Flag D
TGFD
0
1
3
0
R/W
H'FE86
10
[Setting conditions]
[Clearing conditions]
• When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC
• When 0 is written to TGFD after reading TGFD = 1
• When TCNT = TGRD while TGRD is functioning as output compare register
• When TCNT value is transferred to TGRD by input capture signal while
0
Input Capture/Output Compare Flag C
is 0
TGRD is functioning as input capture register
0
1
R/(W)*
TGFC
R/W
2
0
[Clearing conditions]
• When DTC is activated by TGIC interrupt while DISEL bit of MRB in
• When 0 is written to TGFC after reading TGFC = 1
[Setting conditions]
• When TCNT = TGRC while TGRC is functioning as output compare
• When TCNT value is transferred to TGRC by input capture signal
9
0
DTC is 0
register
while TGRC is functioning as input capture register
Up-counter
R/W
R/(W)*
Input Capture/Output Compare Flag B
TGFB
8
0
0
1 [Setting conditions]
1
0
[Clearing conditions]
• When DTC is activated by TGIB interrupt while DISEL bit
• When 0 is written to TGFB after reading TGFB = 1
• When TCNT = TGRB while TGRB is functioning as
• When TCNT value is transferred to TGRB by input
R/W
of MRB in DTC is 0
output compare register
capture signal while TGRB is functioning as input capture
register
7
0
R/(W)*
Input Capture/Output Compare Flag A
TGFA
0
1
0
0
R/W
[Clearing conditions]
• When DTC is activated by TGIA interrupt while
• When DMAC is activated by TGIA interrupt while
• When 0 is written to TGFA after reading TGFA = 1
[Setting conditions]
• When TCNT=TGRA while TGRA is function-
• When TCNT value is transferred to TGRA by
DISEL bit of MRB in DTC is 0
DTA bit of DMABCR in DMAC is 1
6
0
ing as output compare register
input capture signal while TGRA is functioning as
input capture register
R/W
5
0
R/W
4
0
R/W
3
0
TPU3
TPU3
R/W
2
0
R/W
1
0
R/W
0
0