DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 451

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit 1—Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping operation for pulse output group 1 (pins
PO7 to PO4).
Bit 0—Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping operation for pulse output group 0 (pins
PO3 to PO0).
11.2.7
P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1.
Port 1 is multiplexed with pins PO15 to PO8. Bits corresponding to pins used for PPG output must be set to 1. For further
information about P1DDR, see section 9.2, Port 1.
11.2.8
P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 2.
Port 2 is multiplexed with pins PO7 to PO0. Bits corresponding to pins used for PPG output must be set to 1. For further
information about P2DDR, see section 9.3, Port 2.
Bit
Initial value :
R/W
Bit
Initial value :
R/W
Port 1 Data Direction Register (P1DDR)
Port 2 Data Direction Register (P2DDR)
Bit 1
G1NOV
0
1
Bit 0
G0NOV
0
1
:
:
:
:
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR
W
W
7
0
7
0
Description
Normal operation in pulse output group 1 (output values updated at compare match A
in the selected TPU channel)
Non-overlapping operation in pulse output group 1 (independent 1 and 0 output at
compare match A or B in the selected TPU channel)
Description
Normal operation in pulse output group 0 (output values updated at compare match A
in the selected TPU channel)
Non-overlapping operation in pulse output group 0 (independent 1 and 0 output at
compare match A or B in the selected TPU channel)
W
W
6
0
6
0
W
W
5
0
5
0
W
W
4
0
4
0
W
W
3
0
3
0
W
W
2
0
2
0
W
W
Rev.6.00 Oct.28.2004 page 421 of 1016
1
0
1
0
W
W
0
0
0
0
(Initial value)
(Initial value)
REJ09B0138-0600H