DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 231

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.5.4
Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit to 0. In repeat mode,
MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number
of times specified in ETCR. On completion of the specified number of transfers, MAR and ETCRL are automatically
restored to their original settings and operation continues.
One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in
DMACR.
Table 7-8 summarizes register functions in repeat mode.
Table 7-8
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Transfer count register
DTDIR:Data transfer direction bit
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or
decremented by 1 or 2 each time a byte or word is transferred.
IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF.
The number of transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of transfers, when H'00 is
set in both ETCRH and ETCRL, is 256.
In repeat mode, ETCRL functions as the transfer counter, and ETCRH is used to hold the number of transfers. ETCRL is
decremented by 1 each time a transfer is executed, and when its value reaches H'00, it is loaded with the value in ETCRH.
At the same time, the value set in MAR is restored in accordance with the values of the DTSZ and DTID bits in DMACR.
The MAR restoration operation is as shown below.
MAR = MAR – (–1)
Repeat Mode
Register
23
23
Register Functions in Repeat Mode
H'FF
15
MAR
DTID
IOAR
· 2
7
7
ETCRH
DTSZ
ETCRL
· ETCRH
0
0
0
0
DTDIR = 0 DTDIR = 1 Initial Setting
Source
address
register
Destination
address
register
Holds number of
transfers
Transfer counter
Function
Destination
address
register
Source
address
register
Start address of
transfer destination
or transfer source
Start address of
transfer source or
transfer destination
Number of transfers
Number of transfers
Rev.6.00 Oct.28.2004 page 201 of 1016
Operation
Incremented/
decremented every
transfer. Initial
setting is restored
when value reaches
H'0000
Fixed
Fixed
Decremented every
transfer. Loaded with
ETCRH value when
count reaches H'00
REJ09B0138-0600H