DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 170

IC H8S/2300 MCU FLASH 128QFP

DF2398F20V

Manufacturer Part Number
DF2398F20V
Description
IC H8S/2300 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of DF2398F20V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2398F20V
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2398F20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
6.5.6
Figure 6-15 shows the basic access timing for DRAM space. The basic DRAM access timing is 4 states. Unlike the basic
bus interface, the corresponding bits in ASTCR control only enabling or disabling of wait insertion, and do not affect the
number of access states. When the corresponding bit in ASTCR is cleared to 0, wait states cannot be inserted in the
DRAM access cycle.
The 4 states of the basic timing consist of one T
(column address output cycle) states, T
Rev.6.00 Oct.28.2004 page 140 of 1016
REJ09B0138-0600H
Basic Timing
Note: n = 2 to 5
Read
Write
CAS, LCAS
CSn, (RAS)
HWR, (WE)
HWR, (WE)
D
D
A
15
15
23
to D
to D
to A
ø
0
0
0
c1
and T
Figure 6-15 Basic Access Timing
c2
p
.
T
(precharge cycle) state, one T
p
Row
T
r
T
c1
r
(row address output cycle), and two T
Column
T
c2
c

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