DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 247

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

When using the DMAC for single address mode reading, transfer is performed from external memory to the external
device, and the DACK pin functions as a write strobe for the external device. When using the DMAC for single address
mode writing, transfer is performed from the external device to external memory, and the DACK pin functions as a read
strobe for the external device. Since there is no directional control for the external device, one or other of the above single
directions should be used.
Bus cycles in single address mode are in accordance with the settings of the bus controller for the external memory area.
On the external device side, DACK is output in synchronization with the address strobe. For details of bus cycles, see
section 7.5.11, DMAC Bus Cycles (Single Address Mode).
Do not specify internal space for transfer addresses in single address mode.
7.5.9
Basic DMAC Bus Cycles
An example of the basic DMAC bus cycle timing is shown in figure 7-18. In this example, word-size transfer is
performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the
DMAC, a source address read and destination address write are performed. The bus is not released in response to another
bus request, etc., between these read and write operations. As with CPU cycles, DMA cycles conform to the bus
controller settings.
CPU cycle
DMAC cycle (1-word transfer)
CPU cycle
T
T
T
T
T
T
T
T
1
2
1
2
3
1
2
3
ø
Source
Destination address
address
Address bus
RD
HWR
LWR
Figure 7-18 Example of DMA Transfer Bus Timing
The address is not output to the external address bus in an access to on-chip memory or an internal I/O register.
Rev.6.00 Oct.28.2004 page 217 of 1016
REJ09B0138-0600H