DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 258

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after
the DMA write cycle.
DREQ Pin Falling Edge Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1.
Figure 7-31 shows an example of DREQ pin falling edge activated single address mode transfer.
DREQ pin sampling is performed every cycle, with the rising edge of the next ø cycle after the end of the DMABCR write
cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in
the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling
for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA single cycle
ends, acceptance resumes after the end of the single cycle, DREQ pin low level sampling is performed again, and this
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operation is repeated until the transfer ends.
Figure 7-31 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer
Address bus
DMA control
[1]
[2] [5]
[3] [6]
[4] [7]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Channel
DREQ
DACK
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising
edge of ø, and the request is held.
The request is cleared at the next bus break, and activation is started in the DMAC.
Start of DMA cycle; DREQ pin high level sampling on the rising edge of ø starts.
When the DREQ pin high level has been sampled, acceptance is resumed after the single
cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of ø, and the request is held.)
ø
Idle
[1]
Request
Bus release
Minimum of
2 cycles
[2]
[3]
Single
Request clear
DMA single
Transfer source/
period
destination
Acceptance resumes
Idle
[4]
Request
Bus release
Minimum of
2 cycles
[5]
[6]
Single
DMA single
Request clear
Transfer source/
destination
Acceptance resumes
period
Idle
[7]
Bus release