DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 88

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit 7—Reserved: Only 0 should be written to this bit.
Bit 6—Reserved: This bit cannot be modified and is always read as 0.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control mode of the interrupt
controller. For details of the interrupt control modes, see section 5.4.1, Interrupt Control Modes and Interrupt Operation.
Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input.
Bit 2—Reserved: This bit cannot be modified and is always read as 0.
Bit 1—Reserved: Only 0 should be written to this bit.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset status
is released. It is not initialized in software standby mode.
3.2.3
SYSCR2 is an 8-bit readable/writable register that performs on-chip flash memory control.
SYSCR2 is initialized to H'00 by a reset and in hardware standby mode.
SYSCR2 can only be accessed in the F-ZTAT version. In other versions, this register cannot be written to and will return
an undefined value if read.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0.
Rev.6.00 Oct.28.2004 page 58 of 1016
REJ09B0138-0600H
Bit
Initial value :
R/W
System Control Register 2 (SYSCR2) (F-ZTAT Version Only)
Bit 5
INTM1
0
1
Bit 3
NMIEG
0
1
Bit 0
RAME
0
1
:
:
This bit is reserved in the H8S/2390, H8S/2392, H8S/2394, and H8S/2398. Only 0 should be written to
this bit.
—
—
7
0
Bit 4
INTM0
0
1
0
1
Description
An interrupt is requested at the falling edge of NMI input
An interrupt is requested at the rising edge of NMI input
Description
On-chip RAM is disabled
On-chip RAM is enabled
—
—
6
0
Interrupt Control
Mode
0
—
2
—
—
—
5
0
—
—
4
0
Description
Control of interrupts by I bit
Setting prohibited
Control of interrupts by I2 to I0 bits and IPR
Setting prohibited
FLSHE
R/W
3
0
—
—
2
0
—
—
1
0
—
—
0
0
(Initial value)
(Initial value)
(Initial value)