D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 102

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Rev. 2.00 Feb. 12, 2010 Page 18 of 1330
REJ09B0554-0200
Pin No.
N20
P1
P2
P3
P4
P17
P18
P19
P20
R1
R2
R3
R4
R17
R18
R19
R20
T1
T2
T3
T4
T17
T18
T19
T20
U1
U2
U3
U4
U5
U6
U7
Pin Name
IRL0
MFI-INT/LCD_CLK
MFI-CS/LCD_DON
VDD
VSS
VSS
VDD
CAN0_NERR/AUDCK
CAN1_NERR/AUDSYNC
MFI-E/LCD_CL1
MFI-MD/LCD_CL2
CS6
A0
A24
A25
CAN0_RX/AUDATA[2]
CAN1_RX/AUDATA[3]
MFI-RS/LCD_M_DISP
MFI-RW/LCD_FLM
BS
A1
A22
A23
CAN0_TX/AUDATA[0]
CAN1_TX/AUDATA[1]
D0
D15
D3
D11
VSSQ
CKE
VSS
I/O
I
O/I
I/O
⎯
⎯
⎯
⎯
I/O
I/O
I/O
I/O
O
O
O
O
I/O
I/O
I/O
I/O
O
O
O
O
O/O
O/O
IO
IO
IO
IO
⎯
O
⎯
Function
IRL interrupt request 0
MFI interrupt/LCD clock
MFI chip selection/LCD display-on signal
Internal VDD
Internal GND
Internal GND
Internal VDD
HCAN0 bus error signal/H-UDI emulator
HCAN1 bus error signal/H-UDI emulator
MFI enable/ LCD shift clock 1
MFI mode/LCD shift clock 2
Chip select 6
Address bus
Address bus
Address bus
HCAN0 bus data receive signal/H-UDI emulator
HCAN1 bus data receive signal/H-UDI emulator
MFI register select/LCD current-alternating
signal/DISP signal
MFI read/write/LCD first line marker
Bus start
Address bus
Address bus
Address bus
HCAN0 bus data transmit signal/H-UDI emulator
HCAN1 bus data transmit signal/H-UDI emulator
Data bus
Data bus
Data bus
Data bus
IO GND
Clock output enable
Internal GND
GPIO
Ο *
Ο *
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
*
*
*
*
1
1
1
1
1
1