D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 939

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
8
7
6
5
4
Bit Name
TXEM
RXFU
RXHA
RXEM
RXOO
Initial Value
1
0
0
1
0
R/W
R
R
R
R
R/W*
Description
Transmit FIFO Empty Flag
This status flag is enabled only to operation in
FIFO mode. The flag is set to 1 when the transmit
FIFO is empty of data to transmit. It is cleared to 0
when more data is written to the transmit FIFO.
If TXEM = 1 and TEIE = 1 then the interrupt is
generated.
Receive FIFO Full Flag
This status flag is enabled only to operation in
FIFO mode. The flag is set to 1 when the receive
FIFO is full of received bytes and cannot accept
any more. It is cleared to 0 when data is read out of
the receive FIFO.
If RXFU = 1 and RFIE = 1 then the interrupt is
generated.
Receive FIFO Halfway Flag
This status flag is enabled only to operation in
FIFO mode. The flag is set to 1 when the receive
FIFO reaches the halfway point, that is, it has 4
bytes of data and 4 spaces for more data. It is
cleared to 0 when more data is read from the
receive FIFO. It remain set to 1 until cleared to 0
regardless of the subsequent FIFO levels.
If RXHA = 1 and RHIE = 1 then the interrupt is
generated.
Receive FIFO Empty Flag
This status flag is enabled only to operation in
FIFO mode. The flag is set to 1 when the receive
FIFO is empty of received data. It is cleared to 0
when more data is received into to the receive
FIFO.
If RXEM = 0 and RNIE = 1 then the interrupt is
generated.
Receive Buffer Overrun Occurred Flag
This status flag is set to 1 when new data has been
received but the previous received data has not
been read from SPRBR. The previously received
data will not be overwritten by the newly received
data. The RXOO flag remain set to 1 until writing a
0 to its bit position.
If RXOO = 1 and ROIE = 1 then the interrupt is
generated.
Rev. 2.00 Feb. 12, 2010 Page 855 of 1330
REJ09B0554-0200