D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 976

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

The following table shows the relationship between the GPIOIC bits and the corresponding pins to
which interrupts are generated.
When a port pin is used for a GPIO interrupt source, it must be specified for an input pin through
the corresponding port control register. The GPIO interrupt is a low-active level-sensed interrupt.
After a GPIO interrupt is accepted, the GPIO pin level must be retained until the interrupt
processing starts.
The values of the bits specified as GPIO interrupt sources are ORed to detect an interrupt. The bit
that has received an interrupt can be checked by reading the port control registers.
Rev. 2.00 Feb. 12, 2010 Page 892 of 1330
REJ09B0554-0200
Bit
3
2
1
0
Bit Name
PTIREN15
PTIREN14
PTIREN13
PTIREN12
PTIREN11
PTIREN10
PTIREN9
STBRT8
STBRT7
STBRT6
STBIRQ5
STBIRQ4
STBIRL3
STBIRL2
STBIRL1
STBIRL0
Bit Name
STBIRL3
STBIRL2
STBIRL1
STBIRL0
Pin
T2
T1
R2
R1
P2
P1
A13
A14
C18
J20
E2
E1
M19
M20
N19
N20
Initial value
0
0
0
0
USB_PENC
Pin Name
MFI-RW/LCD_FLM
MFI-RS/LCD_M_DISP
MFI-MD/LCD_CL2
MFI-E/LCD_CL1
MFI-CS/LCD_DON
MFI-INT/LCD_CLK
SCIF2_CTS
SCIF2_RTS
FCE/AUDATA[3]
VEPWC/IRQ5
VCPWC/IRQ4
IRL3
IRL2
IRL1
IRL0
R/W
R/W
R/W
R/W
R/W
Description
Standby Cancellation IRL Setting Bit
In standby mode, if an IRL interrupt (IRL is in the
low level) is detected while the corresponding
STBIRL bit is set to 1, the standby mode is
cancelled.
0: Disables canceling standby mode by detection
1: Enables canceling standby mode by detection
of an IRL interrupt
of an IRL interrupt
Port
PTE2
PTE3
PTE6
PTE7
PTH6
PTH5
PTH1
PTK7
PTE0
PTE1
PTE4
PTE5
Interrupt Type
GPIO interrupt
IRQ interrupt
IRL interrupt