D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 977

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

The interrupt source code for the port pins is H'600, except for the IRL and IRQ pins. For the
interrupt source codes for the IRL and IRQ pins and the priority level of the GPIO interrupt, refer
to section 9, Interrupt Controller (INTC).
24.2.22 Port A Pull-Up Control Register (PAPUPR)
PAPUPR is an 8-bit readable/writable register that individually controls the pull-up for pins PTA7
to PTA2 corresponding to each bit in the register when the given pin is used by a peripheral
module. However, for the pins set to the GPIO in the PACR, the settings in this register will be
invalid.
n = 7 to 2
24.2.23 Port B Pull-Up Control Register (PBPUPR)
PBPUPR is an 8-bit readable/writable register that individually controls the pull-up for pins PTB7
to PTB1 corresponding to each bit in the register when the given pin is used by a peripheral
module. However, for the pins set to the GPIO in the PBCR, the settings in this register will be
invalid.
Bit
7
6
5
4
3
2
1, 0 —
Bit Name
PA7PUPR
PA6PUPR
PA5PUPR
PA4PUPR
PA3PUPR
PA2PUPR
Initial Value
1
1
1
1
1
1
All 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
PUPR
PUPR
PA7
PB7
R/W
R/W
7
1
7
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
PUPR
PUPR
PA6
PB6
R/W
R/W
6
1
6
1
PUPR
PUPR
PA5
PB5
Description
Sets individual pull-up control for given pins of Port A
0: PTAn pull-up off
1: PTAn pull-up on
Reserved
These bits are always read as 0, and the write value
should always be 0.
R/W
R/W
5
1
5
1
PUPR
PUPR
PA4
PB4
R/W
R/W
4
1
4
1
PUPR
PUPR
PA3
PB3
R/W
R/W
3
1
3
1
Rev. 2.00 Feb. 12, 2010 Page 893 of 1330
PUPR
PUPR
PA2
PB2
R/W
R/W
2
1
2
1
PUPR
R/W
PB1
R
1
0
1
1
-
R
R
0
0
0
0
-
-
REJ09B0554-0200