D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 852

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

21.3.19 Root Hub Descriptor A Register (HcRhDescriptorA)
HcRhDescriptorA is the first register of two describing the characteristics of the root hub. The
descriptor length (11), descriptor type (TBD), and hub controller current (0) bits in the hub Class
Descriptor are emulated by HCD. All other bits are allocated in HcRhDescriptorA and
HcRhDescriptorB.
Initial value:
Initial value:
Bit
31 to 24
23 to 13
12
Rev. 2.00 Feb. 12, 2010 Page 768 of 1330
REJ09B0554-0200
R/W:
R/W:
Bit:
Bit:
R/W
Bit Name
POTPGT
⎯
NOCP
31
15
R
0
0
-
R/W
30
14
-
R
0
0
R/W
29
13
R
0
0
-
Initial Value
H'02
All 0
1
NOCP
R/W
R/W
28
12
POTPGT
0
1
OCPM
R/W
R/W
27
11
0
0
R/W
DT
26
10
R
0
0
R/W
R/W
R
R/W
R/W
R/W
NPS
25
1
9
1
Description
Power On To Power Good Time
This bit specifies the HCD wait time before
accessing a powered-on port of the root hub. It is
implementation-specific. The unit of time is 2 ms.
The duration is calculated as POTPGT × 2 ms.
Reserved
These bits are always read as 0. Always write 0 to
this bit.
No Overcurrent Protection
This bit describes the overcurrent condition
reporting method for root hub ports. When this bit is
cleared to 0, the OCPM bit specifies either global or
per-port reporting.
0: Overcurrent status info is collected
1: Overcurrent protection is not supported
Note: There are restrictions on this bit. For details,
R/W
R/W
PSM
24
0
8
0
see section 21.6, Restrictions on
HcRhDescriptorA.
23
R
R
0
7
0
-
22
R
R
0
0
6
-
21
R
R
0
5
0
-
20
R
R
0
4
0
-
NDP
19
R
R
0
3
0
-
18
R
R
0
2
0
-
17
R
R
0
1
1
-
16
R
R
0
0
0
-