D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 206

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 6.1
Page table entry high register
Page table entry low register
Page table entry assistance register PTEA
Translation table base register
TLB exception address register
MMU control register
Note:
6.2.1
PTEH can be accessed in longwords from H'FF00 0000 in the P4 area and from H'1F00 0000 in
area 7. PTEH consists of the virtual page number (VPN) and address space identifier (ASID).
When an MMU exception or address error exception occurs, the VPN of the virtual address at
which the exception occurred is set in the VPN bit by hardware. VPN varies according to the page
size, but the VPN set by hardware when an exception occurs consists of the upper 22 bits of the
virtual address which caused the exception. VPN setting can also be carried out by software. The
number of the currently executing process is set in the ASID bit by software. ASID is not updated
by hardware. VPN and ASID are recorded in the UTLB by means of the LDLTB instruction.
After the ASID field in PTEH has been rewritten, a branch instruction to the P0, P3, or U0 area
that uses the updated ASID value should be located at least six instructions after the PTEH update
instruction.
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 122 of 1330
REJ09B0554-0200
Register Name
R/W:
R/W:
Bit:
Bit:
* After exiting hardware standby mode, this LSI enters the power-on reset state caused
Page Table Entry High Register (PTEH)
R/W
R/W
by the RESET pin.
31
15
-
-
Register Configuration (2)
R/W
R/W
30
14
-
-
R/W
R/W
29
13
-
-
VPN
R/W
R/W
28
12
-
-
R/W
R/W
27
11
PTEH
PTEL
TTB
TEA
MMUCR
Abbrev.
-
-
R/W
R/W
26
10
-
-
Undefined
Undefined
Power-on
Reset by
RESET
Pin/WDT/
H-UDI
Undefined
Undefined
Undefined
H'0000 0000 H'0000 0000 Retained
R/W
25
R
-
9
-
0
R/W
24
R
-
8
0
-
VPN
R/W
R/W
Undefined
Undefined
Undefined
Undefined
Retained
23
Manual
Reset by
RESET
Pin/WDT/
Multiple
Exception
7
-
-
R/W
R/W
22
6
-
-
R/W
R/W
21
5
-
-
Retained
Retained
Retained
Retained
Retained
Sleep
by Sleep
Instruction/
Deep Sleep
R/W
R/W
20
4
-
-
ASID
R/W
R/W
19
3
-
-
by
Hardware
R/W
R/W
18
*
2
-
-
Standby
R/W
R/W
Retained
Retained
Retained
Retained
Retained
Retained
by
Software/
Each
Module
17
1
-
-
R/W
R/W
16
0
-
-