D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 710

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 17 Serial Communication Interface with FIFO (SCIF)
(6) When Using the DMAC
When using an external clock as the synchronization clock, after SCFTDR is updated by the
DMAC, an external clock should be input after at least five peripheral clock (Pck) cycles. A
malfunction may occur when the transfer clock is input within four cycles after updating SCFTDR
(see figure 17.23).
SCIF_CLK
t
TDFE
SCIF_TXD
D0
D1
D2
D3
D4
D5
D6
D7
Note: When the SCIF is operated on an external clock, set t > 4.
Figure 17.23 Example of Synchronization Clock Transfer by DMAC
(7) Note on the TEND Flag
In clock synchronous mode, when data is written to the transmit FIFO data register (SCFTDR)
using the DMAC, there are cases where the transmit end flag (SCFSR.TEND) will not be cleared.
Workaround: Applications should read SCFSR.TEND using the following procedure.
1. Verify that the data transfer has completed (CHCR.TE = 1) in the DMAC.
2. Read the TEND flag.
3. If the TEND flag is 1, clear it to 0 and then read the TEND flag again.
4. Use the TEND flag value read out the second time.
Rev. 2.00 Feb. 12, 2010 Page 626 of 1330
REJ09B0554-0200