D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 1220

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

31.3.6
1. Instruction access with post-execution condition, or operand access
2. Instruction access with pre-execution condition
31.3.7
1. When instruction access (pre-execution) is set as a break condition, the program counter (PC)
2. When instruction access (post-execution) is set as a break condition, the program counter (PC)
3. When an instruction access (post-execution) break condition is set for a delayed branch
Rev. 2.00 Feb. 12, 2010 Page 1136 of 1330
REJ09B0554-0200
The flag is set when execution of the instruction that causes the break is completed. As an
exception to this, however, in the case of an instruction with more than one operand access the
flag may be set on detection of the match condition alone, without waiting for execution of the
instruction to be completed.
A. Example 1:
B. Example 2:
The flag is set when the break match condition is detected.
A. Example 1:
B. Example 2:
value saved to SPC in user break interrupt handling is the address of the instruction at which
the break condition match occurred. In this case, a user break interrupt is generated and the
fetched instruction is not executed.
value saved to SPC in user break interrupt handling is the address of the instruction to be
executed after the instruction at which the break condition match occurred. In this case, the
fetched instruction is executed, and a user break interrupt is generated before execution of the
next instruction.
instruction, the delay slot instruction is executed and a user break is effected before execution
of the instruction at the branch destination (when the branch is made) or the instruction two
instructions ahead of the branch instruction (when the branch is not made). In this case, the PC
value saved to SPC is the address of the branch destination (when the branch is made) or the
instruction following the delay slot instruction (when the branch is not made).
100 BT L200 (branch performed)
102 Instruction (operand access break on channel A) → flag not set
110 FADD (FPU exception)
112 Instruction (operand access break on channel A) → flag not set
110 Instruction (pre-execution break on channel A) → flag set
112 Instruction (pre-execution break on channel B) → flag not set
110 Instruction (pre-execution break on channel B, instruction access TLB miss)
Condition Match Flag Setting
Program Counter (PC) Value Saved
→ flag set