D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 873

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

22.4
22.4.1
The diagram of the memory map is shown in Fig. 22.2.
H'000
H'002
H'004
H'006
H'008
H'00A
H'00C
H'020
H'022
H'028
H'02A
H'030
H'032
H'038
H'03A
H'040
H'042
H'048
H'04A
H'050
H'052
H'058
H'05A
H'080
H'082
H'090
Receive data frame pending register 1 (CANRXPR1)
Receive data frame pending register 0 (CANRXPR0)
Remote frame request pending register 1 (CANRFPR1)
Remote frame request pending register 0 (CANRFPR0)
Bit15
Transmit pending request register 1 (CANTXPR1)
Transmit pending request register 0 (CANTXPR0)
Unread message status register 1 (CANUMSR1)
Unread message status register 0 (CANUMSR0)
Mailbox interrupt mask register 1 (CANMBIMR1)
Mailbox interrupt mask register 0 (CANMBIMR0)
Transmit acknowledge register 1 (CANTXACK1)
Transmit acknowledge register 0 (CANTXACK0)
Transmit error
counter (CANTEC)
Abort acknowledge register 1 (CANABACK1)
Abort acknowledge register 0 (CANABACK0)
Timer compare match register (CANTCMR)
Programming model – overview
Memory map
Interrupt request register (CANIRR)
Transmit cancel register 1 (CANTXCR1)
Transmit cancel register 0 (CANTXCR0)
Bit configuration register 1 (CANBCR1)
Bit configuration register 0 (CANBCR0)
Timer counter register (CANTCNTR)
Master control register (CANMCR)
General status register (CANGSR)
Interrupt mask register (CANIMR)
Timer control register (CANTCR)
Receive error counter
Figure 22.2 HCAN2 Memory Map
(CANREC)
Bit0
H'100
H'106
H'108
H'10A
H'10C
H'10E
H'110
H'120
H'140
H'160
H'2E0
H'2F3
H'300
H'4A0
H'4C0
H'4E0
H'4F3
Rev. 2.00 Feb. 12, 2010 Page 789 of 1330
Mailbox-29 control / time stamp/ Data / LAFM
Mailbox-30 control / time stamp/ Data / LAFM
Mailbox-31 control / time stamp/ Data / LAFM
Mailbox-15 control / time stamp/ data / LAFM
Mailbox-16 control / time stamp/ data / LAFM
Mailbox-1 control / time stamp/ data / LAFM
Mailbox-2 control / time stamp/ data / LAFM
Mailbox-3 control / time stamp/ data / LAFM
(BaseID,ExtID,Rtr,Ide,DLC,ATX,DART,MBC)
Mailbox-0 acceptance filter mask
0
2
Mailbox-0 data (8 bytes)
4
6
Mailbox 0 time stamp
Mailbox-0 control
REJ09B0554-0200
1
3
5
7