D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 82

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 26.6
Table 26.7
Section 27 Multifunctional Interface (MFI)
Table 27.1
Table 27.2
Table 27.2
Table 27.3
Table 27.4
Table 27.5
Section 28 User Debug Interface (H-UDI)
Table 28.1
Table 28.2
Table 28.3
Table 28.4
Table 28.4
Table 28.4
Section 29 A/D Converter (ADC)
Table 29.1
Table 29.2
Table 29.2
Table 29.3
Table 29.4
Table 29.5
Table 29.6
Table 29.7
Table 29.8
Section 30 LCD Controller (LCDC)
Table 30.1
Table 30.2
Table 30.2
Table 30.3
Table 30.4
Table 30.5
Table 30.6
Table 30.7
Rev. 2.00 Feb. 12, 2010 Page lxxx of lxxxii
REJ09B0554-0200
Card States in which Command Sequence Is Halted ............................................. 951
MMCIF Interrupt Sources...................................................................................... 990
Pin Configuration ................................................................................................... 999
Register Configuration (1).................................................................................... 1000
Register Configuration (2).................................................................................... 1001
MFI Operations .................................................................................................... 1012
Access to MFIIDX and MFIGSR......................................................................... 1012
Memory Map........................................................................................................ 1013
Pin Configuration ................................................................................................. 1021
Commands Supported by Boundary-Scan TAP Controller.................................. 1024
SDBSR Configuration.......................................................................................... 1024
Register Configuration (1).................................................................................... 1032
Register Configuration (2).................................................................................... 1032
Register Configuration (3).................................................................................... 1033
Pin Configuration ................................................................................................. 1041
Register Configuration (1).................................................................................... 1042
Register Configuration (2).................................................................................... 1042
Analog Input Channels and Corresponding A/D Conversion Data Registers ...... 1043
A/D Conversion Time .......................................................................................... 1054
Relationship between Clock Division Ratio and Usable Input Clock
Frequency............................................................................................................. 1059
AD Conversion Time ........................................................................................... 1060
ADST Transition Period....................................................................................... 1060
Setting between Pck and Clock Division Ratio.................................................... 1061
Pin Configuration ................................................................................................. 1064
Register Configuration (1).................................................................................... 1065
Register Configuration (2).................................................................................... 1066
I/O Clock Frequency and Clock Division Ratio................................................... 1069
Display Resolutions when Using Display Rotation ............................................. 1093
Available Power-Supply Control-Sequence Periods at Typical Frame Rates ...... 1101
LCDC Operating Modes ...................................................................................... 1102
LCD Module Power-Supply States ...................................................................... 1102