D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 145
![IC SUPER H MPU ROMLESS 256BGA](/photos/12/31/123173/d6417760bp200adv_sml.jpg)
D6417760BP200ADV
Manufacturer Part Number
D6417760BP200ADV
Description
IC SUPER H MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D6417760BP200ADV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417760BP200ADV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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• Underflow (U):
• Inexact exception (I): An inexact result is generated.
3.6
The FPU supports two kinds of graphics functions: new instructions for geometric operations, and
pair single-precision transfer instructions that enable high-speed data transfer.
3.6.1
Geometric operation instructions perform approximate-value computations. To enable high-speed
computation with a minimum of hardware, the FPU ignores comparatively small values in the
partial computation results of four multiplications. Consequently, the error shown below is
produced in the result of the computation:
Maximum error = MAX (individual multiplication result ×
The number of significant digits is 24 for a normalized number and 23 for a denormalized number
(number of leading zeros in the fractional part).
In a future version of the SuperH RISC engine family, the above error is guaranteed, but the same
result is not guaranteed.
FIPR FVm, FVn (m, n: 0, 4, 8, 12): This instruction is basically used for the following purposes:
• Inner product (m ≠ n):
• Sum of square of elements (m = n):
Since approximate-value computations are performed to enable high-speed computation, the
inexact exception (I) bit in both the FPU exception cause field and flag field are always set to 1
when an FIPR instruction is executed. Therefore, if the I bit is set in the FPU exception enable
field, FPU exception handling will be executed.
FTRV XMTRX, FVn (n: 0, 4, 8, 12): This instruction is basically used for the following
purposes:
• Matrix (4 × 4) ⋅ vector (4):
When FPSCR.DN = 0, a denormalized number with the same sign as the unrounded value, or
zero with the same sign as the unrounded value, is generated.
When FPSCR.DN = 1, zero with the same sign as the unrounded value, is generated.
This operation is generally used for surface/rear surface determination for polygon surfaces.
This operation is generally used to find the length of a vector.
Graphics Support Functions
Geometric Operation Instructions
2
–MIN (number of multiplier significant digits–1, number of multiplicand significant digits–1)
Rev. 2.00 Feb. 12, 2010 Page 61 of 1330
) + MAX (result value × 2
REJ09B0554-0200
–23
, 2
–149
)
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