D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 742

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

18.5.3
Figure 18.9 shows repetition operations when the smart card interface is in transmitter mode. (1)
to (4) in figure 18.9 correspond to items 1 to 4 described below.
1. After completion of transmission of one frame, if an error signal is returned from the receiver,
2. In T = 0 mode, the TEND bit in SISSR is not set for a frame when an error signal indicating an
3. If no error signal is returned from the receiver, the ERS bit in SISSR is not set.
4. If an error signal is not returned from the receiver, it is assumed that transmission of one
Rev. 2.00 Feb. 12, 2010 Page 658 of 1330
REJ09B0554-0200
Figure 18.9 Repetition Standby Mode (clock stopped) when the Smart Card Interface Is in
the ERS bit in SISSR is set to 1. If the RIE bit in SISCR is set to enable, an SIMERI request is
issued. The ERS bit in SISSR should be cleared to 0 before the sampling timing for the next
parity bit.
error is received.
frame, including repetition, is completed, and the TEND bit in SISSR is set to 1. At this time,
if the TIE bit in SISCR is set to enable, a TEI interrupt request is issued.
TDRE
TEND
ERS
Transmission from SITDR to SITSR
Repetition when the Smart Card Interface Is in Transmitter Mode (T = 0)
Ds
D0 D1 D2 D3 D4 D5 D6 D7 DP
nth transfer frame
DE
(1)
Transmitter Mode
(2)
Ds
D0 D1 D2 D3 D4 D5 D6 D7 DP
Repeat frame
Transmission from SITDR to SITSR
(4)
(3)
(DE)
Ds
D0 D1 D2 D3 D4
n+1th transfer frame