D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 551

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11.6
The DMABRG has independent FIFOs (32-bit 16-stage) for the LCDC, HAC, SSI, and USB with
which it performs DMA transfers between the LCDC, HAC, SSI, and USB and synchronous
DRAM. The DMABRG transfers a maximum of 32-byte data in a single DMA transfer.
11.6.1
DMA transfer by the DMABRG is performed using DMAC channel 0. The independent FIFOs
(32-bit 16-stage) for the LCDC, HAC, SSI, and USB generate DMABRG requests. The LCDC,
HAC, SSI, and USB that are connected to the DMABRG can operate at the same time.
CHCR0*, SAR0, and DAR0 are automatically set according to the LCDC or DMABRG register
settings. CHCR0, SAR0, and DAR0 do not have to be set (rewritten) by the CPU.
Note: * If CHCR0.DE = 1 is set by the CPU, an address error may occur (DMAOR.AE = 1) and
11.6.2
The DMAC of this LSI suspends a DMA transfer when the following conditions are met.
(1) NMI interrupt occurred
(2) DMA address error occurred
When the DMAC suspends a DMA transfer by the above conditions while using the DMABRG
(LCDC, HAC, SSI, or USB), reset the DMABRG (CHCR.CHSET = 1), re-specify the DMAC
registers*, and then reactivate the DMAC.
Setting the BRGRST bit in DMAPCR to 1 resets the DMABRG. The reset is canceled by clearing
the BRGRST bit to 0. Resetting the DMABRG forcibly terminates DMA transfer for the HAC,
SSI, USB, or LCDC. In this case, a transfer end interrupt is not generated.
Resetting the DMABRG initializes the following registers to the state of a power-on reset.
• DMABRGCR
• DMAACR
• DMAUSAR
• DMAUDAR
• DMAURWSZ
• DMAUCR
DMABRG Request
DMABRG Operation
DMABRG Reset
the DMAC will stop operation. When using DMABRG requests, make sure the CPU
does not set CHCR0.DE = 1.
Rev. 2.00 Feb. 12, 2010 Page 467 of 1330
REJ09B0554-0200