D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 1023

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Interrupt control register 0
Interrupt control register 1
Interrupt status register 0
Interrupt status register 1
Transfer clock control register
Command timeout control register
Transfer byte number count register
Mode register
Command type register
Response type register
Response register 0
Response register 1
Response register 2
Response register 3
Response register 4
Response register 5
Response register 6
Response register 7
Response register 8
Response register 9
Response register 10
Response register 11
Response register 12
Response register 13
Response register 14
Response register 15
Response register 16
Data timeout register
Data register
FIFO pointer clear register
Register Name
Abbrev.
INTCR0
INTCR1
INTSTR0
INTSTR1
CLKON
CTOCR
TBCR
MODER
CMDTYR H'00
RSPTYR
RSPR0
RSPR1
RSPR2
RSPR3
RSPR4
RSPR5
RSPR6
RSPR7
RSPR8
RSPR9
RSPR10
RSPR11
RSPR12
RSPR13
RSPR14
RSPR15
RSPR16
DTOUTR
DR
FIFOCLR H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'xxxx
Power-on
Reset by
RESET
Pin/WDT/
H-UDI
H'00
H'00
H'FFFF
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'FFFF
H'xxxx
H'00
Manual Reset
by RESET
Pin/WDT/
Multiple
Exception
Rev. 2.00 Feb. 12, 2010 Page 939 of 1330
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Sleep
by Sleep
Instruction/
Deep Sleep
by
Hardware
*
REJ09B0554-0200
Standby
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
by
Software/
Each
Module