D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 160

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Instruction
CMP/PL
CMP/STR Rm,Rn
DIV1
DIV0S
DIV0U
DMULS.L Rm,Rn
DMULU.L Rm,Rn
DT
EXTS.B
EXTS.W
EXTU.B
EXTU.W
MAC.L
MAC.W
MUL.L
MULS.W
MULU.W
NEG
NEGC
SUB
Rev. 2.00 Feb. 12, 2010 Page 76 of 1330
REJ09B0554-0200
Rn
Rm,Rn
Rm,Rn
Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
@Rm+,@Rn+ Signed, (Rn) × (Rm) + MAC →
@Rm+,@Rn+ Signed, (Rn) × (Rm) + MAC →
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Operation
When Rn > 0, 1 → T
Otherwise, 0 → T
When any bytes are equal,
1 → T
Otherwise, 0 → T
1-step division (Rn ÷ Rm)
MSB of Rn → Q,
MSB of Rm → M, M^Q → T
0 → M/Q/T
Signed, Rn × Rm → MAC,
32 × 32 → 64 bits
Unsigned, Rn × Rm → MAC,
32 × 32 → 64 bits
Rn – 1 → Rn; when Rn = 0,
1 → T
When Rn ≠ 0, 0 → T
Rm sign-extended from
byte → Rn
Rm sign-extended from
word → Rn
Rm zero-extended from
byte → Rn
Rm zero-extended from
word → Rn
MAC
Rn + 4 → Rn, Rm + 4 → Rm
32 × 32 + 64 → 64 bits
MAC
Rn + 2 → Rn, Rm + 2 → Rm
16 × 16 + 64 → 64 bits
Rn × Rm → MACL
32 × 32 → 32 bits
Signed, Rn × Rm → MACL
16 × 16 → 32 bits
Unsigned, Rn × Rm → MACL
16 × 16 → 32 bits
0 – Rm → Rn
0 – Rm – T → Rn, borrow → T
Rn – Rm → Rn
Instruction Code
0100nnnn00010101 —
0010nnnnmmmm1100 —
0011nnnnmmmm0100 —
0010nnnnmmmm0111 —
0000000000011001 —
0011nnnnmmmm1101 —
0011nnnnmmmm0101 —
0100nnnn00010000 —
0110nnnnmmmm1110 —
0110nnnnmmmm1111 —
0110nnnnmmmm1100 —
0110nnnnmmmm1101 —
0000nnnnmmmm1111 —
0100nnnnmmmm1111 —
0000nnnnmmmm0111 —
0010nnnnmmmm1111 —
0010nnnnmmmm1110 —
0110nnnnmmmm1011 —
0110nnnnmmmm1010 —
0011nnnnmmmm1000 —
Privileged
T Bit
Comparison
result
Comparison
result
Calculation
result
Calculation
result
0
—
—
Comparison
result
—
—
—
—
—
—
—
—
—
—
Borrow
—