D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 273

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8.3
8.3.1
Figure 8.1 shows an outline flowchart of the basic operations in instruction execution and
exception handling. For the sake of clarity, the following description assumes that instructions are
executed sequentially, one by one. Figure 8.1 shows the relative priority order of the different
kinds of exceptions (reset, general exception, and interrupt). Register settings in the event of an
exception are shown only for SSR, SPC, SGR, EXPEVT/INTEVT, SR, and PC. However, other
registers may be set automatically by hardware, depending on the exception. For details, see
section 8.5, Operation. Also, see section 8.5.4, Priority Order with Multiple Exceptions, for
exception handling during execution of a delayed branch instruction and a delay slot instruction,
or in the case of instructions in which two data accesses are performed.
Execute next instruction
exception requested?
Exception Flow
Exception Flow
requested?
requested?
General
Interrupt
Reset
No
No
No
Figure 8.1 Instruction Execution and Exception Handling
Yes
SSR ← SR
SPC ← PC
SGR ← R15
EXPEVT/INTEVT ← exception code
SR.{MD,RB,BL} ← 111
PC ← (BRCR.UBDE=1 && User_Break?
Yes
Yes
DBR: (VBR + Offset))
priority exception
re-exception
Is highest-
type?
No
Cancel instruction execution
Yes
result
Rev. 2.00 Feb. 12, 2010 Page 189 of 1330
EXPEVT ← exception code
SR. {MD, RB, BL, FD, IMASK} ← 11101111
PC ← H'A000 0000
REJ09B0554-0200