D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 142

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 3.3
Field Name
Cause
Enable
Flag
3.3.3
Information is transferred between the FPU and CPU via FPUL. FPUL is a 32-bit system register
that is accessed from the CPU side by means of LDS and STS instructions. For example, to
convert the integer stored in general register R1 to a single-precision floating-point number, the
processing flow is as follows:
Rev. 2.00 Feb. 12, 2010 Page 58 of 1330
REJ09B0554-0200
Bit
17 to 12 Cause
11 to 7
6 to 2
1
0
R1 → (LDS instruction) → FPUL → (single-precision FLOAT instruction) → FR1
Floating-Point Communication Register (FPUL)
Bit Name
Enable
Flag
RM1
RM0
FPU exception
cause field
FPU exception
enable field
FPU exception flag
field
Bit Allocation for FPU Exception Handling
Initial Value
All 0
All 0
All 0
0
1
FPU
Error (E)
Bit 17
None
None
R/W
R/W
R/W
R/W
R/W
R/W
Invalid
Operation (V)
Bit 16
Bit 11
Bit 6
Description
FPU Exception Cause Field
FPU Exception Enable Field
FPU Exception Flag Field
When an FPU exception occurs, the bits
corresponding to the FPU exception cause field and
FPU exception flag field are set to 1. Each time an
FPU operation instruction is executed, the FPU
exception cause field is cleared to 0. The FPU
exception flag field remains set to 1 until it is cleared
to 0 by software.
For bit allocations of each field, see table 3.3.
Rounding Mode
These bits select the rounding mode.
00: Round to Nearest
01: Round to Zero
10: Reserved
11: Reserved
Division
by Zero (Z)
Bit 15
Bit 10
Bit 5
Overflow
(O)
Bit 14
Bit 9
Bit 4
Underflow
(U)
Bit 13
Bit 8
Bit 3
Inexact
(I)
Bit 12
Bit 7
Bit 2