PIC18F46J50-I/PT Microchip Technology, PIC18F46J50-I/PT Datasheet - Page 119

• Manufacturer Part Number: PIC18F46J50-I/PT
• Description: IC PIC MCU FLASH 64KB 44-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46J50-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 22
• Ram Memory Size: 3.6875KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• No. Of Pwm Channels: 2
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Interface Type: I2C/SPI/USART/USB
• On-chip Adc: 13-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164330 - MODULE SKT FOR 44TQFP 18F45J10
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REGISTER 8-9:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SSP2IE
R/W-0
SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit
1 = Enabled
0 = Disabled
BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module)
1 = Enabled
0 = Disabled
RC2IE: EUSART2 Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
TX2IE: EUSART2 Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1 = Enabled
0 = Disabled
CTMUIE: Charge Time Measurement Unit (CTMU) Interrupt Enable bit
1 = Enabled
0 = Disabled
TMR3GIE: Timer3 Gate Interrupt Enable bit
1 = Enabled
0 = Disabled
RTCCIE: RTCC Interrupt Enable bit
1 = Enabled
0 = Disabled
BCL2IE
R/W-0
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 (ACCESS FA3h)
W = Writable bit
‘1’ = Bit is set
RC2IE
R/W-0
R/W-0
TX2IE
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F46J50 FAMILY
TMR4IE
R/W-0
CTMUIE
R/W-0
x = Bit is unknown
TMR3GIE
R/W-0
DS39931C-page 119
RTCCIE
R/W-0
bit 0