PIC18F46J50-I/PT Microchip Technology, PIC18F46J50-I/PT Datasheet - Page 76

• Manufacturer Part Number: PIC18F46J50-I/PT
• Description: IC PIC MCU FLASH 64KB 44-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46J50-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 22
• Ram Memory Size: 3.6875KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• No. Of Pwm Channels: 2
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Interface Type: I2C/SPI/USART/USB
• On-chip Adc: 13-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164330 - MODULE SKT FOR 44TQFP 18F45J10
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F46J50 FAMILY
5.2
5.2.1
The microcontroller clock input, whether from an
internal or external source, is internally divided by ‘4’ to
generate four non-overlapping quadrature clocks (Q1,
Q2, Q3 and Q4). Internally, the PC is incremented on
every Q1; the instruction is fetched from the program
memory and latched into the Instruction Register (IR)
during Q4. The instruction is decoded and executed
during the following Q1 through Q4. Figure 5-4
illustrates the clocks and instruction execution flow.
FIGURE 5-4:
EXAMPLE 5-3:
DS39931C-page 76
1. MOVLW 55h
2. MOVWF PORTB
3. BRA SUB_1
4. BSF
5. Instruction @ address SUB_1
Note:
OSC2/CLKO
(RC mode)
PIC18 Instruction Cycle
CLOCKING SCHEME
PORTA, BIT3 (Forced NOP)
OSC1
All instructions are single-cycle, except for any program branches. These take two cycles since the
fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then
executed.
PC
Q1
Q2
Q3
Q4
Q1
CLOCK/INSTRUCTION CYCLE
INSTRUCTION PIPELINE FLOW
Execute INST (PC – 2)
Fetch INST (PC)
Q2
Fetch 1
T
PC
CY
Q3
0
Q4
Execute 1
Fetch 2
T
CY
1
Q1
Fetch INST (PC + 2)
Execute INST (PC)
Q2
Execute 2
Fetch 3
PC + 2
T
CY
2
5.2.2
An “Instruction Cycle” consists of four Q cycles, Q1
through Q4. The instruction fetch and execute are pipe-
lined in such a manner that a fetch takes one instruction
cycle, while the decode and execute takes another
instruction cycle. However, due to the pipelining, each
instruction effectively executes in one cycle. If an
instruction causes the PC to change (e.g., GOTO), then
two cycles are required to complete the instruction
(Example 5-3).
A fetch cycle begins with the PC incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the IR in cycle Q1. This instruction is then decoded
and executed during the Q2, Q3 and Q4 cycles. Data
memory is read during Q2 (operand read) and written
during Q4 (destination write).
Q3
Q4
Execute 3
Fetch 4
T
CY
INSTRUCTION FLOW/PIPELINING
3
Q1
Execute INST (PC + 2)
Fetch INST (PC + 4)
Fetch SUB_1 Execute SUB_1
Flush (NOP)
Q2
PC + 4
T
© 2009 Microchip Technology Inc.
CY
4
Q3
Q4
T
CY
Internal
Phase
Clock
5