PIC18F46J50-I/PT Microchip Technology, PIC18F46J50-I/PT Datasheet - Page 315

IC PIC MCU FLASH 64KB 44-TQFP

PIC18F46J50-I/PT

Manufacturer Part Number
PIC18F46J50-I/PT
Description
IC PIC MCU FLASH 64KB 44-TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets

Specifications of PIC18F46J50-I/PT

Core Size
8-Bit
Program Memory Size
64KB (32K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
PIC18
No. Of I/o's
22
Ram Memory Size
3.6875KB
Cpu Speed
48MHz
No. Of Timers
2
No. Of Pwm Channels
2
Package
44TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
48 MHz
Operating Supply Voltage
2.5|3.3 V
Data Bus Width
8 Bit
Interface Type
I2C/SPI/USART/USB
On-chip Adc
13-chx10-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164330 - MODULE SKT FOR 44TQFP 18F45J10
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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0
18.5.17.3
Bus collision occurs during a Stop condition if:
a)
b)
FIGURE 18-33:
FIGURE 18-34:
© 2009 Microchip Technology Inc.
After the SDAx pin has been deasserted and
allowed to float high, SDAx is sampled low after
the BRG has timed out.
After the SCLx pin is deasserted, SCLx is
sampled low before SDAx goes high.
SDAx
SCLx
PEN
BCLxIF
P
SSPxIF
SDAx
SCLx
PEN
BCLxIF
P
SSPxIF
Bus Collision During a Stop
Condition
BUS COLLISION DURING A STOP CONDITION (CASE 1)
BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDAx asserted low
Assert SDAx
T
BRG
T
BRG
T
BRG
T
BRG
PIC18F46J50 FAMILY
The Stop condition begins with SDAx asserted low.
When SDAx is sampled low, the SCLx pin is allowed to
float. When the pin is sampled high (clock arbitration),
the BRG is loaded with SSPxADD<6:0> and counts
down to 0. After the BRG times out, SDAx is sampled. If
SDAx is sampled low, a bus collision has occurred. This
is due to another master attempting to drive a data ‘0’
(Figure 18-33). If the SCLx pin is sampled low before
SDAx is allowed to float high, a bus collision occurs. This
is another case of another master attempting to drive a
data ‘0’ (Figure 18-34).
SCLx goes low before SDAx goes high,
set BCLxIF
T
BRG
T
BRG
SDAx sampled
low after T
set BCLxIF
‘0’
‘0’
DS39931C-page 315
‘0’
‘0’
BRG
,

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