PIC18F46J50-I/PT Microchip Technology, PIC18F46J50-I/PT Datasheet - Page 420

• Manufacturer Part Number: PIC18F46J50-I/PT
• Description: IC PIC MCU FLASH 64KB 44-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46J50-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 22
• Ram Memory Size: 3.6875KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• No. Of Pwm Channels: 2
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Interface Type: I2C/SPI/USART/USB
• On-chip Adc: 13-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164330 - MODULE SKT FOR 44TQFP 18F45J10
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F46J50 FAMILY
REGISTER 26-6:
REGISTER 26-7:
DS39931C-page 420
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-4
bit 3
bit 2-1
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5-0
Note 1:
WPCFG
R/WO-1
U-1
—
The “Configuration Words page” contains the FCWs and is the last page of implemented Flash memory on
a given device. Each page consists of 1,024 bytes. For example, on a device with 64 Kbytes of Flash, the
first page is 0 and the last page (Configuration Words page) is 63 (3Fh).
Unimplemented: Program the corresponding Flash Configuration bit to ‘1’
MSSPMSK: MSSP 7-Bit Address Masking Mode Enable bit
1 = 7-Bit Address Masking mode enabled
0 = 5-Bit Address Masking mode enabled
Unimplemented: Read as ‘0’
IOL1WAY: IOLOCK One-Way Set Enable bit
1 = IOLOCK bit (PPSCON<0>) can be set once, provided the unlock sequence has been completed.
0 = IOLOCK bit (PPSCON<0>) can be set and cleared as needed, provided the unlock sequence has
WPCFG: Write/Erase Protect Configuration Region Select bit (valid when WPDIS = 0)
1 = Configuration Words page is not erase/write-protected unless WPEND and WPFP<5:0> settings
0 = Configuration Words page is erase/write-protected, regardless of WPEND and WPFP<5:0>
WPEND: Write/Erase Protect Region Select bit (valid when WPDIS = 0)
1 = Flash pages WPFP<5:0> to (Configuration Words page) are write/erase protected
0 = Flash pages 0 to WPFP<5:0> are erase/write-protected
WPFP<5:0>: Write/Erase Protect Page Start/End Location bits
Used with WPEND bit to define which pages in Flash will be write/erase protected.
WPEND
R/WO-1
Once set, the Peripheral Pin Select registers cannot be written to a second time.
been completed
include the Configuration Words page
U-1
—
CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
WO = Write-Once bit
WO = Write-Once bit
‘1’ = Bit is set
‘1’ = Bit is set
R/WO-1
WPFP5
U-1
—
R/WO-1
WPFP4
U-1
—
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
MSSPMSK
R/WO-1
R/WO-1
WPFP3
R/WO-1
WPFP2
U-0
—
© 2009 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
R/WO-1
WPFP1
U-0
—
IOL1WAY
R/WO-1
R/WO-1
WPFP0
(1)
bit 0
bit 0