PIC18F46J50-I/PT Microchip Technology, PIC18F46J50-I/PT Datasheet - Page 200
![IC PIC MCU FLASH 64KB 44-TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18F46J50-I/PT
Manufacturer Part Number
PIC18F46J50-I/PT
Description
IC PIC MCU FLASH 64KB 44-TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18F46J50-I/PT
Core Size
8-Bit
Program Memory Size
64KB (32K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
PIC18
No. Of I/o's
22
Ram Memory Size
3.6875KB
Cpu Speed
48MHz
No. Of Timers
2
No. Of Pwm Channels
2
Package
44TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
48 MHz
Operating Supply Voltage
2.5|3.3 V
Data Bus Width
8 Bit
Interface Type
I2C/SPI/USART/USB
On-chip Adc
13-chx10-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164330 - MODULE SKT FOR 44TQFP 18F45J10
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F46J50-I/PT
Manufacturer:
NXP
Quantity:
3 000
Company:
Part Number:
PIC18F46J50-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F46J50-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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PIC18F46J50 FAMILY
12.7
If ECCP1 or ECCP2 is configured to use Timer1 and to
generate a Special Event Trigger in Compare mode
(CCPxM<3:0> = 1011), this signal will reset Timer3.
The trigger from ECCP2 will also start an A/D conver-
sion if the A/D module is enabled (see Section 17.3.4
“Special Event Trigger” for more information).
The module must be configured as either a timer or a
synchronous counter to take advantage of this feature.
When used this way, the CCPRxH:CCPRxL register
pair effectively becomes a Period register for Timer1.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
Special Event Trigger, the write operation will take
precedence.
FIGURE 12-4:
DS39931C-page 200
Note:
TMR1GE
T1GPOL
T1GVAL
T1G_IN
Timer1
Resetting Timer1 Using the ECCP
Special Event Trigger
T1CKI
The Special Event Trigger from the
ECCPx module will not set the TMR1IF
interrupt flag bit (PIR1<0>).
TIMER1 GATE COUNT ENABLE MODE
N
N + 1
circuitry. This is also referred to as Timer1 gate count
12.8
The Timer1 can be configured to count freely or the count
can be enabled and disabled using the Timer1 gate
enable.
Timer1 gate can also be driven by multiple selectable
sources.
12.8.1
The Timer1 Gate Enable mode is enabled by setting
the TMR1GE bit of the T1GCON register. The polarity
of the Timer1 Gate Enable mode is configured using
the T1GPOL bit of the T1GCON register.
When Timer1 Gate Enable mode is enabled, Timer1
will increment on the rising edge of the Timer1 clock
source. When Timer1 Gate Enable mode is disabled,
no incrementing will occur and Timer1 will hold the
current count. See Figure 12-4 for timing details.
TABLE 12-3:
T1CLK
↑
↑
↑
↑
Timer1 Gate
N + 2
T1GPOL
TIMER1 GATE COUNT ENABLE
0
0
1
1
TIMER1 GATE ENABLE
SELECTIONS
© 2009 Microchip Technology Inc.
T1G
0
1
0
1
N + 3
Counts
Holds Count
Holds Count
Counts
Timer1 Operation
N + 4
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