PIC18F46J50-I/PT Microchip Technology, PIC18F46J50-I/PT Datasheet - Page 316

• Manufacturer Part Number: PIC18F46J50-I/PT
• Description: IC PIC MCU FLASH 64KB 44-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46J50-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 22
• Ram Memory Size: 3.6875KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• No. Of Pwm Channels: 2
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Interface Type: I2C/SPI/USART/USB
• On-chip Adc: 13-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164330 - MODULE SKT FOR 44TQFP 18F45J10
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F46J50 FAMILY
TABLE 18-4:
DS39931C-page 316
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
PIR3
PIE3
IPR3
TRISC
TRISB
SSP1BUF
SSPxADD
SSPxMSK
SSPxCON1
SSPxCON2
SSPxSTAT
SSP2BUF
SSP2ADD
Legend:
Note 1:
Name
2:
3:
(1)
— = unimplemented, read as ‘0’. Shaded cells are not used by the MSSPx module in I
SSPxMSK shares the same address in SFR space as SSPxADD, but is only accessible in certain I
operations in 7-Bit Masking mode. See Section 18.5.3.4 “7-Bit Address Masking Mode” for more details.
Alternate bit definitions for use in I
These bits are only available on 44-pin devices.
MSSP1 Receive Buffer/Transmit Register
MSSP1 Address Register (I
MSSP2 Receive Buffer/Transmit Register
MSSP2 Address Register (I
GIE/GIEH PEIE/GIEL
PMPIF
PMPIE
PMPIP
OSCFIF
OSCFIE
OSCFIP
TRISC7
SSP2IF
SSP2IE
SSP2IP
TRISB7
WCOL
GCEN
GCEN
MSK7
Bit 7
SMP
REGISTERS ASSOCIATED WITH I
(3)
(3)
(3)
ACKSTAT
ACKSTAT ADMSK5
TRISC6
TRISB6
BCL2IF
BCL2IE
BCL2IP
SSPOV
CM2IF
CM2IE
CM2IP
MSK6
ADIF
ADIE
ADIP
Bit 6
CKE
2
TMR0IE
TRISC5
TRISB5
SSPEN
ACKDT
CM1IE
CM1IP
2
RC1IF
RC1IE
RC1IP
CM1IF
RC2IF
RC2IE
RC2IP
C™ Slave mode), MSSP1 Baud Rate Reload Register (I
MSK5
C Slave mode), MSSP2 Baud Rate Reload Register (I
Bit 5
D/A
2
C Slave mode operations only.
(2)
ADMSK4
TRISC4
TRISB4
ACKEN
INT0IE
USBIE
USBIP
USBIF
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
MSK4
Bit 4
CKP
P
2
(2)
C™ OPERATION
ADMSK3
TMR4IE
TMR4IP
SSP1IE
SSP1IP
TMR4IF
TRISC3
TRISB3
SSP1IF
BCL1IF
BCL1IE
BCL1IP
SSPM3
RCEN
MSK3
RBIE
Bit 3
S
(2)
ADMSK2
CTMUIE
CTMUIP
CTMUIF
TMR0IF
CCP1IF
CCP1IE
CCP1IP
HLVDIE
HLVDIP
TRISC2
HLVDIF
TRISB2
SSPM2
MSK2
Bit 2
PEN
R/W
(2)
ADMSK1
TMR3GIF
TMR3GIE
TMR3GIP
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
TRISC1
TRISB1
SSPM1
INT0IF
© 2009 Microchip Technology Inc.
RSEN
MSK1
Bit 1
UA
2
2
C Master mode)
C Master mode)
2
(2)
C™ mode.
RTCCIE
RTCCIP
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
RTCCIF
TRISC0
TRISB0
SSPM0
MSK0
RBIF
Bit 0
SEN
SEN
BF
2
C Slave mode
on Page:
Values
Reset
64, 67
64, 67
64, 67
64, 67
64, 67
65
65
65
66
63
65
65
65
65
65
65
66
65
67
67