PIC18F46J50-I/PT Microchip Technology, PIC18F46J50-I/PT Datasheet - Page 365

• Manufacturer Part Number: PIC18F46J50-I/PT
• Description: IC PIC MCU FLASH 64KB 44-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46J50-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 22
• Ram Memory Size: 3.6875KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• No. Of Pwm Channels: 2
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Interface Type: I2C/SPI/USART/USB
• On-chip Adc: 13-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164330 - MODULE SKT FOR 44TQFP 18F45J10
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE 21-2:
TABLE 21-3:
© 2009 Microchip Technology Inc.
Legend: (E) = Even transaction buffer, (O) = Odd transaction buffer
BDnSTAT
BDnCNT
BDnADRL
BDnADRH
Note 1:
Endpoint
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
Name
2:
3:
4:
(1)
(1)
(1)
(1)
For buffer descriptor registers, n may have a value of 0 to 63. For the sake of brevity, all 64 registers are
shown as one generic prototype. All registers have indeterminate Reset values (xxxx xxxx).
Bits 5 through 2 of the BDnSTAT register are used by the SIE to return PID<3:0> values once the register
is turned over to the SIE (UOWN bit is set). Once the registers have been under SIE control, the values
written for DTSEN and BSTALL are no longer valid.
Prior to turning the buffer descriptor over to the SIE (UOWN bit is cleared), bits 5 through 2 of the
BDnSTAT register are used to configure the DTSEN and BSTALL settings.
This bit is ignored unless DTSEN = 1.
(No Ping-Pong)
Out
10
12
14
16
18
20
22
24
26
28
30
0
2
4
6
8
ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT
BUFFERING MODES
Mode 0
SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS
UOWN
Bit 7
11
13
15
17
19
21
23
25
27
29
31
In
1
3
5
7
9
DTS
Bit 6
(Ping-Pong on EP0 OUT)
0 (E), 1 (O)
(4)
Out
13
15
17
19
21
23
25
27
29
31
11
3
5
7
9
Mode 1
PID3
Bit 5
(2)
BDs Assigned to Endpoint
10
12
14
16
18
20
22
24
26
28
30
32
In
2
4
6
8
PID2
Buffer Address High
Buffer Address Low
Bit 4
12 (E), 13 (O)
16 (E), 17 (O)
20 (E), 21 (O)
24 (E), 25 (O)
28 (E), 29 (O)
32 (E), 33 (O)
36 (E), 37 (O)
40 (E), 41 (O)
44 (E), 45 (O)
48 (E), 49 (O)
52 (E), 53 (O)
56 (E), 57 (O)
60 (E), 61 (O)
(2)
Byte Count
PIC18F46J50 FAMILY
0 (E), 1 (O)
4 (E), 5 (O)
8 (E), 9 (O)
(Ping-Pong on all EPs)
Out
DTSEN
PID1
Bit 3
Mode 2
(2)
(3)
14 (E), 15 (O)
18 (E), 19 (O)
22 (E), 23 (O)
26 (E), 27 (O)
34 (E), 35 (O)
38 (E), 39 (O)
42 (E), 43 (O)
46 (E), 47 (O)
50 (E), 51 (O)
54 (E), 55 (O)
58 (E), 59 (O)
62 (E), 63 (O)
10 (E), 11 (O)
30 (E), 31 (O) 26 (E), 27 (O) 28 (E), 29 (O)
2 (E), 3 (O)
6 (E), 7 (O)
In
BSTALL
PID0
Bit 2
(2)
(3)
(Ping-Pong on all other EPs,
10 (E), 11 (O) 12 (E), 13 (O)
14 (E), 15 (O) 16 (E), 17 (O)
18 (E), 19 (O) 20 (E), 21 (O)
22 (E), 23 (O) 24 (E), 25 (O)
34 (E), 35 (O) 36 (E), 37 (O)
38 (E), 39 (O) 40 (E), 41 (O)
42 (E), 43 (O) 44 (E), 45 (O)
46 (E), 47 (O) 48 (E), 49 (O)
50 (E), 51 (O) 52 (E), 53 (O)
54 (E), 55 (O) 56 (E), 57 (O)
58 (E), 59 (O) 60 (E), 61 (O)
30 (E), 31 (O) 32 (E), 33 (O)
2 (E), 3 (O)
6 (E), 7 (O)
Out
0
Bit 1
BC9
except EP0)
DS39931C-page 365
Mode 3
4 (E), 5 (O)
8 (E), 9 (O)
Bit 0
BC8
In
1