PIC18F46J50-I/PT Microchip Technology, PIC18F46J50-I/PT Datasheet - Page 185

• Manufacturer Part Number: PIC18F46J50-I/PT
• Description: IC PIC MCU FLASH 64KB 44-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46J50-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 22
• Ram Memory Size: 3.6875KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• No. Of Pwm Channels: 2
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Interface Type: I2C/SPI/USART/USB
• On-chip Adc: 13-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164330 - MODULE SKT FOR 44TQFP 18F45J10
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

10.4
This section introduces some potential applications for
the PMP module.
FIGURE 10-27:
10.4.2
Partial multiplexing implies using more pins; however,
for a few extra pins, some extra performance can be
achieved. Figure 10-28 provides an example of a
memory or peripheral that is partially multiplexed with
FIGURE 10-28:
FIGURE 10-29:
© 2009 Microchip Technology Inc.
Application Examples
PIC18F
PIC18F
PIC18F
PARTIALLY MULTIPLEXED
MEMORY OR PERIPHERAL
PMD<7:0>
PMD<7:0>
PMD<7:0>
PMALH
PMALL
PMALL
PMWR
PMWR
PMRD
PMALL
PMRD
PMCS
PMCS
PMWR
PMCS
PMRD
MULTIPLEXED ADDRESSING APPLICATION EXAMPLE
EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION
EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION
AD<7:0>
ALE
CS
RD
WR
373
373
373
Parallel Peripheral
A<15:8>
A<7:0>
D<7:0>
D<7:0>
A<7:0>
PIC18F46J50 FAMILY
10.4.1
Figure 10-27 demonstrates the hookup of a memory or
another addressable peripheral in Full Multiplex mode.
Consequently, this mode achieves the best pin saving
from the microcontroller perspective. However, for this
configuration, there needs to be some external latches
to maintain the address.
an external latch. If the peripheral has internal latches,
as displayed in Figure 10-29, then no extra circuitry is
required except for the peripheral itself.
MULTIPLEXED MEMORY OR
PERIPHERAL
A<7:0>
D<7:0>
CE
A<13:0>
D<7:0>
CE
OE
OE
WR
WR
Address Bus
Data Bus
Control Lines
Address Bus
Data Bus
Control Lines
Address Bus
Data Bus
Control Lines
DS39931C-page 185