PIC18F46J50-I/PT Microchip Technology, PIC18F46J50-I/PT Datasheet - Page 57

• Manufacturer Part Number: PIC18F46J50-I/PT
• Description: IC PIC MCU FLASH 64KB 44-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46J50-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 22
• Ram Memory Size: 3.6875KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• No. Of Pwm Channels: 2
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Interface Type: I2C/SPI/USART/USB
• On-chip Adc: 13-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164330 - MODULE SKT FOR 44TQFP 18F45J10
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

4.0
The PIC18F46J50 Family of devices differentiate
among various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
i)
j)
This section discusses Resets generated by MCLR,
POR and BOR, and covers the operation of the various
start-up timers.
FIGURE 4-1:
© 2009 Microchip Technology Inc.
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during power-managed modes
Watchdog
execution)
Configuration Mismatch (CM)
Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
Deep Sleep Reset
MCLR
Note 1: The Brown-out Reset is not available in PIC18F2XJ50 and PIC18F4XJ50 devices.
V
DD
RESET
Deep Sleep Reset
Pointer
Stack
Configuration Word Mismatch
PWRT
Timer
Brown-out
INTRC
( )_IDLE
V
Time-out
32 ms
Reset
DD
Detect
WDT
Sleep
Rise
External Reset
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Stack Full/Underflow Reset
(1)
RESET Instruction
(WDT)
POR Pulse
PWRT
11-Bit Ripple Counter
Reset
66 ms
(during
PIC18F46J50 FAMILY
For information on WDT Resets, see Section 26.2
“Watchdog Timer (WDT)”. For Stack Reset events,
see Section 5.1.4.4 “Stack Full and Underflow
Resets” and for Deep Sleep mode, see Section 3.6
“Deep Sleep Mode”.
Figure 4-1 provides a simplified block diagram of the
on-chip Reset circuit.
4.1
Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the register
indicate that a specific Reset event has occurred. In
most cases, these bits can only be set by the event and
must be cleared by the application after the event. The
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in Section 4.7 “Reset State of
Registers”.
RCON Register
S
R
Q
DS39931C-page 57
Chip_Reset